yxs33 / lms-adaptive-filter-as-hardware-accelerator

Implementation of LMS Adaptive filter on hardware FPGA board as well as in software NIOS II processor.

LMS-Adaptive-Filter-as-Hardware-Accelerator

This project is based on FPGA/DSP. The main objective of this project is to implement and design LMS Adaptive filter on hardware FPGA board as well as in software NIOS II processor.
Implementation of LMS Adaptive filter in software (Qsys with NIOS II processor Eclipse) and as a hardware accelerator on FPGA board.
It shows clear comparision regarding the performance of software as well as hardware. Compared performance between software and hardware designs shows that Hardware Accelerator is more efficient as it consumes less cycles to calculate output. As it gives effective result in less time, it is called Hardware Accelerator.
Thus, LMS Adaptive filter can be used as Hardware Accelerator on FPGA board.
Here, I have attached whole report of this project which includes necessary design codes as well as resultant output with conclusion.

Tools: Altera Quartus Prime, Qsys, ModelSim, MATLAB.
You can also use Xilinx Vivado tool for design and simulation.

Programming language: Verilog.

FPGA Hardware development kit: Altera DE0 Nano SoC board/Altera DE1 FPGA board.

Project Report file: LMS_HW_Acc.pdf (includes whole project)