Yash Keswani
Ritika Nagar
Hardik Patel
Repository for Computer Organization, Monsoon 2021 semester, assignment at IIITD
Current progress: Assembler Done! Simulator Done!
Contains assembler and simulator for the given RISC ISA, made in Python.
add and sub are already given. see if you can do any else!
remember that you can perform OR, LSL, LSR, etc. with just one simple line of code. [bitwise operators!!]
If you see the template for the code you'll see that I have added test cases and tips there. Please write as much of the function as you can understand.
send a pull request when you're done. default template present in the file.
once again, check for comments in the program file. They'll help a lot.
template present in the file. send a pull request when done.
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