xilinx / vitis_model_composer

Vitis Model Composer Examples and Tutorials

Rapid design exploration using Vitis Model Composer

Within the Simulink environment, Vitis Model Composer offers a range of performance-optimized blocks that facilitate the design and implementation of DSP algorithms on AMD devices. The inclusion of the Vitis Model Composer AI Engine, HLS, and HDL libraries enables efficient algorithm exploration and greatly expedites the path towards production.

To learn more, visit the Vitis Model Composer website.

Where should you start?

Are you interested in accelerating your development effort using Vitis Model Composer? Here is where to start:

• Review the supported operating systems and MATLAB releases.
• Learn the basics of Simulink. To use Vitis Model Composer effectively, you need to understand the basics of Simulink, a block diagram environment for multidomain simulation and model-based design.
• Go over to the tutorials. The tutorials will give you a solid understanding of how to use the tool.
• Browse through many of the examples we have here. You can easily access these examples from within the tool. (Note: Many of the examples require the DSP System Toolbox.)

What's new in 2024.1?

• The Normalization example showcases two features of the AIE-ML architecture: shared buffers on memory tiles, and the bfloat16 data type.
• See a 64K-pt IFFT at 2 GSPS implemented in AI Engine using a 2D architecture.
• Working with both AI Engines and PL? See the tutorials showing how to connect the block libraries in Vitis Model Composer.
• MATLAB R2023a and R2023b are now supported by Vitis Model Composer.

Examples

Tutorials

Quick Guides

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Copyright 2024 Advanced Micro Devices, Inc.

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

vitis_model_composer's Issues

Running_BOOT_BIN_on_Hardware

When you click on the link for How to Install Hardware Server on step 7 in this guide,

it takes you to the same location. Please change the link for How to Install Hardware Server on step 7 to https://github.com/Xilinx/Vitis_Model_Composer/blob/main/QuickGuides/Running_BOOT_BIN_on_Hardware/README.md#how-to-install-hardware-server

Lab6 - XPAR_LAB6_1_0_DEVICE_ID in hello_world_final.c is not declared

XPAR_LAB6_1_0_DEVICE_ID in hello_world_final.c (line 237) is not declared anywhere. I tried XPAR_HDL_DUT_0_DEVICE_ID instead, but that is also not declared anywhere.

Example HDL: AXI DDS Compiler, Simulink period set to 1 despite frequency is 1Mhz

Hello, I want to check the output frequency of DDS with spectrum analyzer. But the example told to set Simulink period in Vitis hub settings to 1. This causes spectrum analyzer to show signal frequency incorrectly.
I really can't understand why this tutorial creator set the Simulink period to 1 instead of 1/100e6 to help fully see output frequency. Setting that to 1 only creates ambiguity, doesn't it?
Though I've set Simulink period to 1/100e6 and the output of DDS became 0.
Any help will be appreciated.

lab6_1.h is missing

I am trying to use your lab6 example to do some co-simulation using the kv260 starter kit, but I noticed lab6_1.h file is missing.

Is SysGen now VitisModelComposer

I have questions about Vitis Model Composer.

• Is Sysgen rebranded to Vitis Model Composer, or are they 2 different products?
• Will HDL-Coder work with Vitis Model Composer / is it necessary?
• I would like to interface with FMCOMMS3 with my generated design, will this be possible?

Thank you!

Sine wave HDL bug: output data can't be spectrum analyzed

By having this: Sinewave -> output gateway -> spectrum analyzer
Hub setting: zynq7000-7020-400-2, FPGA period:1e9/125e6 Simulink period: 1/125e6
Output is visible in scope but not in spectrum analyzer. DSP spectrum analyzer shows nothing, but by checking the propagate data type to output we can see that also in spectrum analyzer, why?