High-level synthesis is an automated design process that takes an abstract behavioral specification of a digital system and find a register-transfer level structure that realizes the given behavior.
Optimization done using HLS pragmas.
- Matrix size: 100x100
- Inputs: Generated and filled with random numbers in the testbench.
- Target device: Artix7 100t (xa7a100t-csg324-1I)
- Create a vitis project.
- The opt_tb.c is equivalent of a "testbench" and should be added as a simulation source. It is common for both cases.
- The other two files are sources. Add one of them as a source and run simulation and synthesis. Repeat with the other source file.
Frequency | Cycles | LUT | FF | DSP |
---|---|---|---|---|
144.77 Mhz | 1110001 | 558 | 591 | 3 |
Frequency | Cycles | LUT | FF | DSP |
---|---|---|---|---|
144.59 Mhz | 16051 | 1872321 | 747503 | 300 |