weston-embedded / uc-os2 Goto Github PK

in the os_core.c, the line 1919, usage = 100 - (INT8S)(OSIdleCtrRun / OSIdleCtrMax);
OSCPUUsage = 100 *(1- OSIdleCtr / OSIdleCtrMax) Isn't that the formula you provided?

In the call to OSMemCreate(), if arg checking is enabled, the pointer to the start of the partition is cast to an integer in order to verify its aligned to store pointers.

When I compile this on a 64bit system I get compiler warnings about the cast to a smaller type. uC-CPU defines an OS_ADDR type, which would be ideal to use here, but uC-OS2 isn't required to use it. My workaround so far has been to add a similar typedef in os_cpu.h (along with the others like INT32U currently used in the cast).

To reproduce; compile os_mem.c on Ubuntu 18.04 (64bit) using gcc 7.5.0.

Can any one Knows, how to port to Cortex-M23 Controller. OS-2 Port is missing for the Same.

I am using Ports/PPC440 and qemu-system-ppc to learn more about uC-OS2. Tasks are running but I don't get OSTickISR to happen. I see in file os_cpu_a.S there is:

.org _vectorbase + 0x0700
DEC_ISR: OSTickISR

and

   lis     4,  _vectorbase@h                           /* Initialize the IVPR register                */
    ori   4, 4,  _vectorbase@l
    mtivpr  4
    mtivor0 4

    addi     4, 4, IVOR1_VAL
    mtivor1 4

    addi     4, 4, SIXTEEN_BYTES
    mtivor2 4
...
...
   addi     4, 4, SIXTEEN_BYTES
    mtivor10 4

Above initializes IVPR and IVOR10

I may then also need to enable interrupts though it seems this is done in the stack frame of new uC-OS2 tasks in os_cpu_c.c

    /* Interrupts will be enabled when the task is started           */
    msr    |= 0x00028000;

Do I would need to load an initial value in the decrement register (possibly w/ auto-reloading)? How does one do this? Is there code example (either for PPC440 or related) that I can use to see how to enable OSTickISR? The uC-OS2 book says on page 389:

Because we didnt enable interrupts nor did we start the clock tick, OSTimeDly(1) will never return to
TestTask() !

But I can't figure out how to get OSTickISR to happen. Any hints and pointers welcome. Thanks.

I run my compiled binary with:

qemu-system-ppc -M bamboo -cpu 440epb -nographic -kernel test.elf -s

and my Linkmap is:

ENTRY(_Reset)
SECTIONS
{
. = 0x10000;
startup : { startup.o(.text)}
.data : {*(.data)}
.bss : {*(.bss)}
. = . + 0x500;
sp_top = .;
}

#define FLAG_UNLOCKED ((OS_FLAGS)0x0001)

OS_FLAG_GRP *flag_group;

void WorkWithSharedResource()
{
    INT8U err;

    // 1: Start of critical section
    OSFlagPend(flag_group, FLAG_UNLOCKED, (OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME), 0, &err);

    // 2: start long-running operation, wait semaphore (signaled in interrupt)
    OSSemPend(...)

    // 3: end of critical section
    OSFlagPost(flag_group, FLAG_UNLOCKED, OS_FLAG_SET, &err)
}

// high priority task
void TaskA(void *p_arg)
{
   while (true)
   {
       WorkWithSharedResource();
   }
}

// low priority task
void TaskB(void *p_arg)
{
   while (true)
   {
       WorkWithSharedResource();
   }
}

Conditions:
flag_grp->flags contains FLAG_UNLOCKED (i.e. bit is set)

Steps:

1. 1A - high priority task acquire flag (because flag is set)
2. 2A - high priority task start pend on semaphore
3. context switch to TaskB
4. 1B - low priority task start pend (flag is not set, TaskA consumed it in step 1)
5. semaphore signaled by interrupt, TaskA become ready, context switch to TaskA
6. 3A - high priority task set flag (in that step TaskB become ready through pgrp->OSFlagWaitList traversal)
7. 1A - TaskA continues execution, it's priority is higher than TaskB. So 'FLAG_UNLOCKED' will be acquired again.
8. 2A - TaskA pend on semaphore
9. context switch to TaskB
10. OSFlagPend continues execution in believing that flag group contains 'FLAG_UNLOCKED' flag (because of OSTCBCur->OSTCBFlagsRdy), but it's not.
    So, TaskA and TaskB in critical section, race condition...

Hi,

license.txt seems to be just some kind of license header, where you claim, that the source code is under Apache-2.0, but not the license itself. The Apache-2.0 license requires in 4(a):
"You must give any other recipients of the Work or Derivative Works a copy of this License; and" ...

But there is no copy of the license.

I would suggest to concatenate the text from https://www.apache.org/licenses/LICENSE-2.0.txt at the bottom of "license.txt" (just a link is not sufficient!) to comply to the license.

This should be necessary for all "uC-..." repositories.

This would help all the users of the source code at license scanning and to become license compliant.

Thank you.

Regards, Thorsten

Increasing priority using a write to BASEPRI does not take effect immediately.
(a) IMPLICATION This erratum means that the instruction after an MSR to boost BASEPRI
might incorrectly be preempted by an insufficient high priority exception.

(b) WORKAROUND The MSR to boost BASEPRI can be replaced by the following code sequence:

CPSID i
MSR to BASEPRI
DSB
ISB
CPSIE i

Hello everyone! I am working on implementing a tool to assess the complexity of CPU architecture porting. It primarily focuses on RISC-V architecture porting. As part of my dataset, I have collected the rt-thread project. By using scanning tools, I have determined that the porting complexity is high due to a significant amount of code related to the CPU architecture. It would require a professional team to handle this task. Is this assessment accurate? I look forward to your help and response.

Is the current version provided here susceptible to the vulnerability described here?
https://us-cert.cisa.gov/ics/advisories/icsa-21-119-04

It references "Micrium uCOS II/uCOS III Versions 1.39.0 and prior". This is a very old version, or is this a typo, or is it referring to a sub-module?

Thanks for your help sorting this out.

Hello everyone! I am working on implementing a tool to assess the complexity of CPU architecture porting. It primarily focuses on RISC-V architecture porting. As part of my dataset, I have collected the uC-OS2 project. By using scanning tools, I have determined that the porting complexity is high due to a significant amount of code related to the CPU architecture. It would require a professional team to handle this task. Is this assessment accurate? I look forward to your help and response.

I am interested in ports/PowerPC/* ports. All of these (and in fact many other ports) all refer to a file "cpu.h" that I can't find anywhere in the repo. I tried to search this situation on google but can't find any solution.

Where would one find this file? I am using GNU gcc toolchain for ppc 32 bits big endian to do my compiling - no file cpu.h in that toolchain either.

In the OSTimeTick function, is there some problem with where the critical section function is used?: