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FPGA-based Ultra-High Throughput JPEG-LS encoder, which provides lossless image compression. 一个超高性能的FPGA JPEG-LS编码器,用来进行无损图像压缩。

Home Page: https://gitee.com/wangxuan95/UH-JLS

License: GNU General Public License v3.0

SystemVerilog 64.89% Verilog 35.04% Batchfile 0.07%
fpga image-compression image-encoder jpeg-ls verilog

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uh-jls's Issues

Image data cannot be transferred to the processing module

你好!UH_LS模块,在修改“INPUT_PGM_DIR”和“OUTPUT_JLS_DIR”的路径为自己电脑对应文件夹路径时,仿真结束后会出现.jls文件,但是用网站打开却什么都看不到,仿真波形输出为0,请问这是啥原因?谢谢回复!

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