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View Code? Open in Web Editor NEWAn open-source custom cache generator.
License: BSD 3-Clause "New" or "Revised" License
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problems in run "python3 opencache.py config_file"
my config_file.py is:
# Data array size
total_size = 1024
# Data word bit size
word_size = 8
# Number of words per line
words_per_line = 4
# Address port size
address_size = 11
# Number of ways
num_ways = 1
# Replacement policy
replacement_policy = None
# Write policy
write_policy = "write-back"
# Output file name
output_name = "cache"
openram_options = {
"tech_name": "scn4m_subm",
"nominal_corner_only": True,
"analytical_delay": False,
}
# For simulation
simulate = True
# For synthesis
synthesize = True
# To keep the results
keep_temp = True
when I run "python3 opencache.py config_file", error information is
** Start: 04/26/2022 18:32:54
Cache type: Data
Word size: 8
Words per line: 4
Number of ways: 1
Replacement policy: None
Write policy: Write-back
Return type: Word
Data hazard: True
Saving output files...
Config: Writing to /home/zk/opencache/generator/outputs/cache/cache_data_array_config.py
Config: Writing to /home/zk/opencache/generator/outputs/cache/cache_tag_array_config.py
** Config: 0.0 seconds
Verilog: Writing to /home/zk/opencache/generator/outputs/cache/cache.v
Traceback (most recent call last):
File "opencache.py", line 56, in <module>
c.save()
File "/home/zk/opencache/generator/cache/cache.py", line 72, in save
self.verilog_write(vpath)
File "/home/zk/opencache/generator/cache/cache.py", line 47, in verilog_write
self.c.verilog_write(path)
File "/home/zk/opencache/generator/base/design.py", line 46, in verilog_write
ports=ports)
File "/home/zk/.local/lib/python3.6/site-packages/amaranth/back/verilog.py", line 51, in convert
verilog_text, name_map = convert_fragment(fragment, name, emit_src=emit_src)
File "/home/zk/.local/lib/python3.6/site-packages/amaranth/back/verilog.py", line 42, in convert_fragment
return _convert_rtlil_text(rtlil_text, strip_internal_attrs=strip_internal_attrs), name_map
File "/home/zk/.local/lib/python3.6/site-packages/amaranth/back/verilog.py", line 13, in _convert_rtlil_text
yosys = find_yosys(lambda ver: ver >= (0, 10))
File "/home/zk/.local/lib/python3.6/site-packages/amaranth/_toolchain/yosys.py", line 228, in find_yosys
raise YosysError("Could not find an acceptable Yosys binary. The `amaranth-yosys` PyPI "
amaranth._toolchain.yosys.YosysError: Could not find an acceptable Yosys binary. The `amaranth-yosys` PyPI package, if available for this platform, can be used as fallback
could you help me, thank you very much!
Bypass registers aren't used sometimes
If a cache is supposed to use bypass registers at a cycle and SRAM outputs match the request (for instance, SRAM outputs are hit although bypass registers are not), bypass registers are not used.
OpenRAM Failed error
Hi, i was trying to generate a basic cache (the one described in README file). This is the config file:
# Data array size
total_size = 1024
# Data word bit size
word_size = 8
# Number of words per line
words_per_line = 4
# Address port size
address_size = 11
# Number of ways
num_ways = 1
# Replacement policy
replacement_policy = None
# Write policy
write_policy = "write-back"
# Output file name
output_name = "cache"
# Add this to OpenCache config file
openram_options = {
"tech_name": "sky130A",
"nominal_corner_only": True,
"analytical_delay": False,
}
# For simulation
simulate = True
# For synthesis
synthesize = True
# To keep the results
keep_temp = True
Then i execute the command: python3 opencache.py my_config.py inside generator folder. The output is:
** Start: 07/06/2022 22:21:32
Cache type: Data
Word size: 8
Words per line: 4
Number of ways: 1
Replacement policy: None
Write policy: None
Return type: Word
Data hazard: True
Saving output files...
Config: Writing to /home/gabriele/OpenCache/generator/outputs/cache/cache_data_array_config.py
Config: Writing to /home/gabriele/OpenCache/generator/outputs/cache/cache_tag_array_config.py
** Config: 0.0 seconds
Verilog: Writing to /home/gabriele/OpenCache/generator/outputs/cache/cache.v
** Verilog: 0.1 seconds
Initializing verification...
ERROR: file verification.py: line 167: OpenRAM failed!
Traceback (most recent call last):
File "opencache.py", line 61, in <module>
verify.run(cache_config=conf, name=OPTS.output_name)
File "/home/gabriele/OpenCache/generator/verify/__init__.py", line 34, in run
ver.verify()
File "/home/gabriele/OpenCache/generator/verify/verification.py", line 48, in verify
self.prepare_files()
File "/home/gabriele/OpenCache/generator/verify/verification.py", line 144, in prepare_files
self.run_openram("{}_config.py".format(OPTS.temp_path + OPTS.data_array_name))
File "/home/gabriele/OpenCache/generator/verify/verification.py", line 167, in run_openram
debug.error("OpenRAM failed!", -1)
File "/home/gabriele/OpenCache/generator/debug.py", line 47, in error
assert return_value == 0
AssertionError
I also tried to modify simulate = True to simulate = False but nothing changes.
Can't get OpenCache to work
When I try to run OpenCache on the default config files, I'm getting this error:
nachiket in generator git:(dev*) 24-03-14 11:56AM python3 opencache.py tests/configs/config.py
|==============================================================================|
|========= OpenCache v0.0.1 =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= Computer Science and Engineering Department =========|
|========= University of California Santa Cruz =========|
|========= =========|
|========= Usage help: [email protected] =========|
|========= Development help: [email protected] =========|
|========= See LICENSE for license info =========|
|==============================================================================|
** Start: 03/14/2024 11:56:59
Cache type: Data
Word size: 32
Words per line: 4
Number of ways: 1
Replacement policy: None
Write policy: None
Return type: Word
Data hazard: True
Saving output files...
Config: Writing to /home/nachiket/OpenCache/generator/outputs/unit_test/cache_8192b_32b_1_none/cache_8192b_32b_1_none_data_array_config.py
Config: Writing to /home/nachiket/OpenCache/generator/outputs/unit_test/cache_8192b_32b_1_none/cache_8192b_32b_1_none_tag_array_config.py
** Config: 0.0 seconds
Verilog: Writing to /home/nachiket/OpenCache/generator/outputs/unit_test/cache_8192b_32b_1_none/cache_8192b_32b_1_none.v
Traceback (most recent call last):
File "opencache.py", line 56, in <module>
c.save()
File "/home/nachiket/OpenCache/generator/cache/cache.py", line 72, in save
self.verilog_write(vpath)
File "/home/nachiket/OpenCache/generator/cache/cache.py", line 47, in verilog_write
self.c.verilog_write(path)
File "/home/nachiket/OpenCache/generator/base/design.py", line 41, in verilog_write
ports = self.add_io_signals()
File "/home/nachiket/OpenCache/generator/base/design.py", line 107, in add_io_signals
self.flush = cache_signal()
File "/home/nachiket/.local/lib/python3.8/site-packages/amaranth/hdl/ast.py", line 1075, in __call__
signal = super().__call__(shape, **kwargs, src_loc_at=src_loc_at + 1)
TypeError: __init__() got an unexpected keyword argument 'src_loc_at'
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