AIM:
To implement the given logic function verify its operation in Quartus using Verilog programming.
F1= A’B’C’D’+AC’D’+B’CD’+A’BCD+BC’D
F2=xy’z+x’y’z+w’xy+wx’y+wxy
Equipment Required:
Hardware – PCs, Cyclone II , USB flasher
Software – Quartus prime
Theory
Logic Diagram
Procedure
-
Type the program in Quartus software.
-
Compile and run the program.
-
Generate the RTL schematic and save the logic diagram.
-
Create nodes for inputs and outputs to generate the timing diagram.
-
For different input combinations generate the timing diagram.
Program:
module boolean(A,B,C,D,F1);
input A,B,C,D;
output F1;
wire x1,x2,x3,x4,x5;
assign x1=(~A)&(~B)&(~C)&(~D);
assign x2=(A)&(~C)&(~D);
assign x3=(~B)&(C)&(~D);
assign x4=(~A)&(B)&(C)&(D);
assign x5=(B)&(~C)&(D);
assign F1=x1|x2|x3|x4|x5;
endmodule
Developed by: VIGNESH V RegisterNumber:212223110062
Thus the given logic functions are implemented using and their operations are verified using Verilog programming.