Comments (4)
Reported by jeffrey.goeders
on 2012-04-30 04:51:45
- Labels added: Module-VPR
from vtr-verilog-to-routing.
Reported by JasonKaiLuu
on 2012-06-04 21:52:50
from vtr-verilog-to-routing.
Is this due to running out of memory?
Reported by jeffrey.goeders
on 2012-06-04 22:07:00
from vtr-verilog-to-routing.
Miscounted amount of memory needed. Fixed.
Reported by JasonKaiLuu
on 2012-06-05 17:45:03
- Status changed:
Fixed
from vtr-verilog-to-routing.
Related Issues (20)
- Document how to test QoR for NoC designs HOT 2
- Detailed NoC Usage (Latency Etc.) Report
- Failed routing due to unusable stratix10_arch.xml
- Pin-to-pin direct connection between tiles
- Error at parsing the results of a task HOT 2
- parse_vtr_flow doesn't follow documentation
- Problems in compiling the latest VTR HOT 3
- VPR Placer runtime issue when all design clusters have fixed locations HOT 6
- Run-flat on Koios Benchmark HOT 1
- Router Lookahead File Extension Error Handling HOT 3
- Change RRG storage to keep (drive pt, direction) instead of (start, end)
- Try setting first_iter_pres_fac to a value > 0 HOT 1
- Designs with many different wire types fail at certain channel widths with an arithmetic exception
- Clean up rr_node_route_inf HOT 4
- Add wire length attribute to RR graph output XML when using "--write_rr_graph" option
- CI Test Failures on Master HOT 3
- Failed to build target 'libarchfpga' HOT 1
- Disabling CAPNPROTO Crashes Build
- clang/LLVM-17 build HOT 4
- Remove Warnings in VTR CI Builds
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