Comments (3)
Working on it
from fundamental.
ADSR graphics fixed.
from fundamental.
Oh right, forgot to close
from fundamental.
Related Issues (20)
- Default version in Rack-2 SDK helper.py should be 2.0.0 not 1.0.0 HOT 1
- Duplicating WT VCO does not copy its contents HOT 1
- paramQuantity in VCA.cpp and Octave.cpp not found HOT 2
- Trigger source set to "External" by default HOT 1
- WT VCO does something horrible if you change wave points after loading HOT 1
- Fundamental VCO outputs much, much more aliasing in analog mode than digitial mode.
- VCO-1 The pulse wave has a lot of DC on the output in digital mode
- VCO Sqr does not output channel 13-16
- WT VCO does not load wav set in user preset
- WT VCO locks mutex too often/too long in the GUI thread
- SEQ 3 Suggestion: Copy / Paste Column
- **SOLUTION** Fundamental VCO Pops and Clicks from PWM
- Release v2.1.0 source HOT 1
- Switch 1-4 As Clock Modulator/Gate Router
- SCOPE Buffer size too small
- SCOPE feature request: repurpose trigger input for blanking control when in XY mode
- Incorrect regex in helper.py HOT 1
- Add S&H tag to the VCV Process module.
- 2.5.1 build failure on Fedora 39 with gcc 13.2.1 HOT 3
- ADSR: stages duration does not match fader values
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from fundamental.