Implementation of combinational logic gates
To implement the given logic function verify its operation in Quartus using Verilog programming. F1= A’B’C’D’+AC’D’+B’CD’+A’BCD+BC’D F2=xy’z+x’y’z+w’xy+wx’y+wxy
Hardware – PCs, Cyclone II , USB flasher,Software – Quartus prime
Logic gates are electronic circuits which perform logical functions on one or more inputs to produce one output.
- Create a project with required entities.
- Create a module along with respective file name.
- Run the respective programs for the given boolean equations.
- Run the module and get the respective RTL outputs.
- Create university program(VWF) for getting timing diagram.
- Give the respective inputs for timing diagram and obtain the results.
Program to implement the given logic function and to verify its operations in quartus using Verilog programming.
Developed by: Vasanthamukilan.M
RegisterNumber: 212222230167
*/
module Combinational(A,B,C,D,W,X,Y,Z,F1,F2);
input A,B,C,D,W,Y,X,Z;
output F1,F2;
wire A1,A2,A3,A4,A5,B1,B2,B3,B4,B5;
assign A1 = ((~A)&(~B)&(~C)&(~D));
assign A2 = (A&(~C)&(~D));
assign A3 = ((~B)&C&(~D));
assign A4 = ((~A)&B&C&D);
assign A5 = (B&(~C)&D);
assign B1 = (X&(~Y)&Z);
assign B2 = ((~X)&(~Y)&Z);
assign B3 = ((~W)&X&Y);
assign B4 = (W&(~X)&Y);
assign B5 = (W&X&Y);
assign F1 = (A1|A2|A3|A4|A5);
assign F2 = (B1|B2|B3|B4|B5);
endmodule
Thus the given logic functions are implemented using and their operations are verified using Verilog programming.