Comments (3)
@dabelknap, can you try compiling things on l1ts-rct-01? You need to bounce through cms904usr to get there. Probably you need to checkout from github while on cms904usr, l1ts-rct-01 is not connected to the net.
from cms-calo-layer1.
softipbus
and cms-calo-level1
compile. Is that all we need for this issue?
from cms-calo-layer1.
Yes :)
from cms-calo-layer1.
Related Issues (20)
- Test SPIStream via oRSC inter-FPGA echo test HOT 2
- caen::write() does not do what we think HOT 2
- oRSC Back-End Doesn't Reach "main()" HOT 2
- Ensure we can read out link status from the CTP6 FE at 904 HOT 5
- /opt/AMC13/ecad_activate_amc13.sh needs python 2.6 at 904 HOT 3
- Validate instructions on updating BSPs using Xilinx GUI HOT 1
- Document how to recover from Xilinx "JTAG Cable not Found" error HOT 5
- oRSC Locks up VME HOT 32
- update issue #4 ... readout link status @ chmbln HOT 33
- Address items requested by L1 SW code review
- oRSC FE SPI XIntc_Connect Jumps to Command 'DEADBEEF' HOT 18
- Can't make blinky lights on oRSC HOT 3
- VMEStream Echo Test HOT 9
- Write standalone uart backend application for oRSC HOT 4
- Failed to open JTAG Cable for CTP6 HOT 9
- oRSC uart ECHO test (working at Chmberlin) HOT 4
- ASIO reported a Timeout in TCP callback HOT 10
- Put VMEStream in cms-calo-layer1 package HOT 4
- Write orsc_fe_vmestream_echo_test and validate VMEStream HOT 6
- Write oRSC BE VMEStream -> SPIStream code HOT 7
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