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RISC-V also has a extension for compressed instructions (2-byte). Currently those are not supported, because capstone does not disassemble them correctly.

There is a pull-request, which merges the necessary changes:
capstone-engine/capstone#1594

So we have to wait until this one is merged.

I'm using riscv64 to analyze a binary from Favourite Architecure challenge series in *CTF https://adworld.xctf.org.cn/media/uploads/task/c11db24e682f4d4d802f4a3ca9ca76b8.zip.

As you can see, 0x10546 supposed to be a branch instruction.

I'll gladly help if you could point me where should I take a look first.

We started working on RISC-V 64-bit, but it is only somewhat supported currently.

The most major issue is that both architectures cannot be registered on the ELF machine type at the same type, due to a limitation of the current BN api (see Vector35/binaryninja-api#1553)

orthogonally, we need to go through all the RV64 specific instructions and make sure they are lifted correctly.

Currently we do not lift any of the FP instructions. We should change that.

• define FP registers
• lift FP load/store (should work)
• lift FP arithmetic instructions