Request for example to connect normal UART and JTAG to IO pin on Arty100T FPGA about chipyard

[jerryz123]

The arty100t design uses the on-board USB-UART for the UART-TSI link.
To support another UART/JTAG interface, we'd need to allocate one of the PMODs.
Which PMOD would you prefer?

[T-K-233]

Could we use the following mapping on PMOD JD?

• JD0 (Pin 1) - TDO
• JD1 (Pin 2) - (nTRST)
• JD2 (Pin 3) - TCK
• JD3 (Pin 4) - UART_TXD
• JD4 (Pin 7) - TDI
• JD5 (Pin 8) - TMS
• JD6 (Pin 9) - (nRESET)
• JD7 (Pin 10) - UART_RXD

[T-K-233]

Also here's the bump signal - pin names mapping:

[jerryz123]

@T-K-233 can you fix the mapping in what you posted? It looks like the available pins are 1-4, and 7-10, not 0-7.

[T-K-233]

Oh, I'm using the Chisel port IO index. Corrected above.