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asp-dac24-tutorial

This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024

atom

:atom: The hackable text editor

berkeleyabc.jl

Julia wrapper for the Berkeley logic synthesis and verification program ABC

caravel_board

ci-fusesoc-action

LibreCores CI Github Action with FuseSoC driven flow

circuit_training

csil

A Python platform for experiments with ABC, Yosys, and OpenSTA

dctk

Delay Calculation ToolKit

dolly

dreamplace

Deep learning toolkit-enabled VLSI placement

drexel-ecec575

fastercap_v2

fault

A complete open-source design-for-testing (DFT) Solution

gcloud_test

lighter

An automatic clock gating utility

openlane

NOTE: The master branch is frozen for OpenMPW2. Please direct any PRs to the develop branch. :: OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

openroad

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

openroad-flow-scripts

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

opensta_sta_workshop

pythonechoserver

rlc-circuit-mor

Implementation of modified nodal analysis and model order reduction of RLC circuits

serv

SERV - The SErial RISC-V CPU

siliconcompiler

A modular build system for hardware

super-star-trek

This is the original 1978 BASIC Source code for the classic text-only Super Star Trek Game.

vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

yosys-openroad-plugins

Plugins developed for Yosys by the Open Road Project.