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Intel 8080 emulator core, written in Lua

Home Page: https://tobiasvl.github.io/optable/intel-8080/

License: MIT License

Lua 100.00%
emulator 8080 intel8080 intel-8080 intel-8080-emulator lua lua-library i8080

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lua-8080's Issues

Disassembler misses a DAA

No idea what causes this (I can't reproduce it in a smaller program), but when running 8080EXM.COM the DAA at cycle 86712065 is mistakenly disassembled as a NOP. (It's still executed correctly.)

To reproduce:

tvl@rocinante:~/src/lua-8080 $ luajit main.lua 8080EXM.COM debug
tvl@rocinante:~/src/lua-8080 $ grep -C 2 86712065 debug.log
PC: 0D54, AF: 9A06, BC: 9079, DE: 8D5B, HL: 299D, SP: 0111, CYC: 86712044 (F9 2A A2 0D) - SPHL
PC: 0D55, AF: 9A06, BC: 9079, DE: 8D5B, HL: 299D, SP: 299D, CYC: 86712049 (2A A2 0D 27) - LHLD #A20D
PC: 0D58, AF: 9A06, BC: 9079, DE: 8D5B, HL: A559, SP: 299D, CYC: 86712065 (27 00 00 00) - NOP
PC: 0D59, AF: 0017, BC: 9079, DE: 8D5B, HL: A559, SP: 299D, CYC: 86712069 (00 00 00 22) - NOP
PC: 0D5A, AF: 0017, BC: 9079, DE: 8D5B, HL: A559, SP: 299D, CYC: 86712073 (00 00 22 A2) - NOP

Pass 8080EXER.COM 

dad <b,d,h,sp>................  PASS! crc is:14474ba6
aluop nn......................  PASS! crc is:9e922f9e
aluop <b,c,d,e,h,l,m,a>.......  PASS! crc is:cf762c86
<daa,cma,stc,cmc>.............  ERROR **** crc expected:bb3f030c found:12da49a1
<inr,dcr> a...................  PASS! crc is:adb6460e
<inr,dcr> b...................  PASS! crc is:83ed1345
<inx,dcx> b...................  PASS! crc is:f79287cd
<inr,dcr> c...................  PASS! crc is:e5f6721b
<inr,dcr> d...................  PASS! crc is:15b5579a
<inx,dcx> d...................  PASS! crc is:7f4e2501
<inr,dcr> e...................  PASS! crc is:cf2ab396
<inr,dcr> h...................  PASS! crc is:12b2952c
<inx,dcx> h...................  PASS! crc is:9f2b23c0
<inr,dcr> l...................  PASS! crc is:ff57d356
<inr,dcr> m...................  PASS! crc is:92e963bd
<inx,dcx> sp..................  PASS! crc is:d5702fab
lhld nnnn.....................  PASS! crc is:a9c3d5cb
shld nnnn.....................  PASS! crc is:e8864f26
lxi <b,d,h,sp>,nnnn...........  PASS! crc is:fcf46e12
ldax <b,d>....................  PASS! crc is:2b821d5f
mvi <b,c,d,e,h,l,m,a>,nn......  PASS! crc is:eaa72044
mov <bcdehla>,<bcdehla>.......  PASS! crc is:10b58cee
sta nnnn / lda nnnn...........  PASS! crc is:ed57af72
<rlc,rrc,ral,rar>.............  PASS! crc is:e0d89235
stax <b,d>....................  PASS! crc is:2b0471e9
Tests complete
real    51m46.682s
user    51m31.391s
sys     0m0.531s

Really need to optimize to debug this test...

Optimize bus

Turns out my bus implementation is inefficient. Not a good place for a bottleneck...

I still need it to be modular, but the current way I do it, ie. with a memory_map table where the key is a table with start address and length, isn't good – even though the memory map is usually small, pairs is un-JIT-able.

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