tmsimont / cache-simulator Goto Github PK

somewhere in the cache, cache set, or cache block code, an exception is thrown on read and/or write when cache associativity is greater than 1

The Address class looks like it has the index, tag and offset properties on it

This was a mistake I made in the UML.

The Cache needs to tell you what the index, tag and offset of an address are, because L1 and L2 will have different values for these properties for the same address. So, the address itself can't know what it's tag, offset or index is because these properties are specific to each cache.

For example, if L1 is 2-way associative, it only needs 1 bit for index.

If L2 is 4-way associative in the same architecture, then it will have to use 2 bits of the address to index the set.

This would bean that the tag size is different for the two caches is the same architecture.

So I think we need

std::bitset Cache::getTag(Address a);

for each of these three properties

Sorry to generate confusion with the bad UML

In a direct mapped configuration with L2 size >> L1 size, the L2 cache is never generating hits on an L1 miss, so the advantage of two level cache is not realized. Likely this is an issue with fundamental cache writing/reading code AND/OR an error in the way cache hierarchy is written on misses

I was unable to compile the project with g++ without making some minor modifications.

VS C++ compiler is a little more forgiving and Microsoft provides some special functions.

creating new instances of the address class for passing around addresses causes memory leaks due to used, no-longer-referenced, and not deleted address instances

address class should likely be converted to a static class with static method for convenient address calculations given cache parameters, with no actual instances of address class