A processor my partner and I created in verilog for our computer organization class. It is compatible with most of the RISC-V base ISA. The top module can either read in VMH files or 32bit RISC-V instructions. Includes gcd.vmh (greatest common divisor) and fibonacci.vmh. Outputs are specified in top_tb.v.
thezhe / single_cycle_risc-v_processor Goto Github PK
View Code? Open in Web Editor NEWA processor my partner (Nathan Ackermann) and I created in verilog for our computer organization class. It is compatible with most of the RISC-V base ISA.
License: GNU General Public License v3.0