Comments (5)
Fix the underlying problem
It is telling you that your LEF has one rule that overrides another. It isn't an OR problem per se but we don't have to warn about it.
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Fixed by The-OpenROAD-Project/OpenROAD#4813
from openroad-flow-scripts.
@maliberty what about [WARNING DRT-0323] Via(s) in pin VDD of Element will be ignored
from openroad-flow-scripts.
Let's make it a separate issue. @osamahammad21 can comment in the new issue about the impact of this warning (does it imply drc checking issues?)
from openroad-flow-scripts.
Let's make it a separate issue. @osamahammad21 can comment in the new issue about the impact of this warning (does it imply drc checking issues?)
Broke out issue for the second warning: #1862
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Related Issues (20)
- Restore repair_antennas for nangate45/bp_multi
- Switch manual macro placement by mpl2 flow on mock-array
- MACRO_PLACE_HALO doesn't allow specifying a different x & y halo
- Consistent treatment of flag variables HOT 2
- Standard cell placement under power straps with same metal as standard cell pins causing obstructions for route. HOT 103
- VIA Routing over VIA Obstruction HOT 5
- Bug in ihp-sg13g2 jpeg flow HOT 14
- Integration of SRAM macros HOT 15
- Platform SG13G2 misses antenna diode definition in the LEF HOT 13
- Error in building locally in WSL docker HOT 3
- make file error HOT 4
- Error in ” make DESIGN_CONFIG=./designs/asap7/aes/config.mk” cts.tcl HOT 2
- Questions about cell selection and padding. HOT 8
- Error when executing setup.sh on RHEL8
- 请教
- OOM in Global placement asap7/aes-block HOT 2
- Excute yosys returns an error message HOT 4
- Could I have an idea how to start from Gatenetlsit in Openroad-flow-script? HOT 5
- Error when running build_openroad.sh HOT 2
- make synth should fail on syntax error in .lib file HOT 1
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