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branchnet

Source Code for training and evaluating BranchNet models for branch prediction

design-a-cpu-using-risc-v-isa-with-pipeline-and-branch-predictor-unit

dv-cpu-rv

A harvard architecture CPU based on RISC-V.

dynamicbranchprediction

Implementation of 2-bit dynamic branch prediction in a RISC-V processor

epc-gen2-rfid-tag-baseband-processor

Verilog library of EPC Gen-2 RFID Tag Baseband Processor for IC and FPGA designers

fast_intr_cpu

fedar-f1-rv64im

5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.

fifo

包括同步FIFO（输入输出位宽相同），异步FIFO（输入输出位宽相同），异步FIFO（能实现输出数据位宽是输入数据位宽的1/2或2倍）

fpga

数字IC相关资料

ncsu-low-power-rfid

Verilog code for a low power RFID chip that will communicate with I2C sensors.

rfid-reader-ip-core-with-id-filtering-function-

This repository stores a Verilog model of Digital Baseband (DBB) of the RFID reader IC. The standard is specified in EPCTM Radio-Frequency Identity Protocols Class-1 Generation-2 UHF RFID Protocol for Communications at 860 MHz – 960 MHz Version 1.0.9.

risc-v-processor-with-pipelining

Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and multi cycle instructions, ALU unit works in parallel with a multiplication unit, and Reorder Buffer to guarantee in-order termination.

riscv_core

building 32bit risc-v core and Machine Learning for Branch Prediction

simulated-annealing-algorithm-for-vlsi

Simulated annealing algorithm for VLSI floorplanning problem

verilog_library

HYF's high quality verilog codes