sven0601 Goto Github PK
Name: Sven
Type: User
Bio: FPGA designer
Location: HangZhou, China
Name: Sven
Type: User
Bio: FPGA designer
Location: HangZhou, China
System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
To verify the SPI Master IP using the APB and SPI AVIPs
The RIFFA development repository
a very simple risc_cpu verification demo with uvm
RISC-V CPU Core (RV32IM)
an open source uvm verification platform for e200 (riscv)
A quick SPI BFM to assist in SPI device testing and development
A simple SPI master
A SPI design (supporting APB interfaces) using Systemverilog from VG_CPU project
The Tcl Core. (Mirror of core.tcl-lang.org)
A quick UART BFM
UVM testing suite for the SimpRisc CPU
A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology
Source code repo for UVM Tutorial for Candy Lovers
uvm AXI BFM(bus functional model)
Reference examples and short projects using UVM Methodology
Simulation and functional verification of a MIPS processor using UVM.
Verilog PCI express components
AXI Interconnect
Websites for Rikka apps.
Xilinx Tcl Store
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Bring data to life with SVG, Canvas and HTML. 📊📈🎉
JavaScript (JS) is a lightweight interpreted programming language with first-class functions.
Some thing interesting about web. New door for the world.
A server is a program made to process requests and deliver data to clients.
Machine learning is a way of modeling and interpreting data that allows a piece of software to respond intelligently.
Some thing interesting about visualization, use data art
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Open source projects and samples from Microsoft.
Google ❤️ Open Source for everyone.
Alibaba Open Source for everyone
Data-Driven Documents codes.
China tencent open source team.