stanfordaha / lake

Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory macros.

Lake: An Agile Framework for Designing and Automatically Configuring Physical Unified Buffers

Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory macros. Lake also comprises a library of generalized hardware modules aimed at memory controller designs.

Install

git clone github.com/StanfordAHA/lake

cd lake && pip install -e .

Run a test

To run a test, you can simply generate the verilog and push through your favorite verilog simulator. Alternatively, Lake uses the pytest framework for unit tests of constituent modules. These tests leverage fault and verilator for open source simulation. Tests should run and pass on Linux and MacOS.

Documentation

Check out the wiki of this github repo.

lake's Issues

Control signal polarity in tech maps

Specific to dual_port_sram_joey branch:

Tech maps should capture whether each of the control signals is active high or active low to be more generic.

data_out takes in chain_data after stencil valid is gated

The current logic design is shown below:

always_comb begin
  if (accessor_output[0]) begin
    data_out_tile[0] = curr_tile_data_out[0];
  end
  else data_out_tile[0] = chain_data_in[0];
  if (accessor_output[1]) begin
    data_out_tile[1] = curr_tile_data_out[1];
  end
  else data_out_tile[1] = chain_data_in[1];
end

If the chain_data is not driven, which is often the case given our apps, data_out becomes x after valid cycles. As shown in the wave below:

Stencil Valid Config Parsing Error

Why we need to make this change ?08066a1
This lead to an issue when I use the wrapper generator for clockwork sim.

Since it already get the key value of stencil_valid at the place that call it.

lake/lake/top/memtile_builder.py

Line 589 in 86e4520

ctrl_config['stencil_valid'] = mode_map['stencil_valid'].get_bitstream(config_json['stencil_valid'])

Wrapper for verilog generation does not work?

@kavyasreedhar I'm trying the command you recommended to run the verilog wrapper generator, but I'm getting a weird error:

dhuff@kiwi:~/lake$ python tests/wrapper_lake.py -c conv_3_3_recipe/buf_inst_input_10_to_buf_inst_output_3_ubuf 
Traceback (most recent call last):
  File "tests/wrapper_lake.py", line 5, in <module>
    from lake.utils.util import generate_lake_config_wrapper
ImportError: No module named lake.utils.util

Any idea what I'm doing wrong?

Improving Opal 4/22/24

1. Balancing the read scanner crd and seg
2. static segmentation in the GLB read mem
3. Skipping in the intersect "galloping"
4. Stream version of the dense scanner in the sparse flow

Deprecate SRAMMacroInfo and remove it from lake top inputs

Specific to dual_port_sram_joey branch:
SRAMMacroInfo is replaced by the tech map.

Error out with ncsim

As of a89c091, the top test errors out with ncsim, but passes with Verilator. I'm suspecting it's x related issue since Verilator doesn't handle x. It could also be timing/cycle related bug.

Create a chain of and gate use reduce in Kratos

I am trying to use kratos to generate the accessor hardware.

This combinational logic in piece_sel function is to "and" a bunch of bool variables produced by the comparison logic. And doing a log operation on it. I get the following error when run this hardware generator. Could any Kratos expert told me which part I wrote is incorrect?

File "basic.py", line 65, in init
self.add_code(self.piece_sel)
File "/nobackup/joeyliu/aha/lakeenv/lib/python3.7/site-packages/kratos/generator.py", line 558, in add_always
fn_ln, kargs)
File "/nobackup/joeyliu/aha/lakeenv/lib/python3.7/site-packages/kratos/pyast.py", line 848, in transform_stmt_block
exec(code_obj, _globals)
File "", line 10, in
File "", line 5, in piece_sel
File "", line 5, in
_kratos.exception.InvalidConversionException: Cannot convert a variable to bool

Default __main__ missing/old

For debugging purpose it's very helpful to have __main__ in each module so that we can directly inspect the SystemVerilog if things go wrong. Most of the modules already have it, but some of them are either missing, or out-dated. @kavyasreedhar can you do updates on your modules?

Looping Structures don't fire last action when schedule stride > 1.

Looping structures aren't firing their last action when the last action is separated from the previous by more than a cycle.

Chaining logic needs disable

We need to properly disable chaining for single tile apps.

Requesting test for @Kuree

New Memory Tile Feature to Support Unified Buffer

• Input access pattern
• Support Line buffer with correct access pattern
• Support High dimensional stencil width parameter or general stencil valid generation
• Support Arbitrary Delay / Negative starting address
• handle accumulation Buffer with mutiple port

Check about refactoring config code for wrapper?

PR: #70

clk_en bypass for SRAM

To support SRAM configuration while clk_en is low (stall high), we need to use the config_en wires to the SRAM features as a bypass to clk_en for the tile.

Config Sequencer not getting clock under tile_en == 0

In lake_top.py, the clock to the configuration time read/write module to SRAM doesn't get a toggling clock when tile_en is low!