snehith-namgiri / physical-design-implementation-of-4-bit-full-adder-using-cadence

Physical Design Implementation of 4-bit Full Adder Using Cadence

• This is a simple mini project in which I have implemented physical Design of a 4-bit Full Adder. The main objective behind this project is to get a good knowlwdge on Cadence Tool Suite.

• In this project, I have used various Cadence tools for the implementation of Physical Design and get familiar with the TCL and SDC commands.

Tools Used:

• Cadence NC Launch - For Verilog Simulation
• Cadence Genus - For Synthesis and Generation of Netlist.
• Cadence Innovus - For Physical Design