slade-liu / legv8-processor

ARMLEGv8Processor

This project involves the creation of a detailed design and layout of an ARM LEGv8 processor. Given a set of unique instructions for the processor to perform, the data path of each class of instruction as well as the overall datapath of the processor was constructed. Efficient control logic was developed in order support each given instruction, along with a precise and detailed functional table that makes control implementable in a field-programmable gate array (FPGA). In order to perform these specific instructions for the ARM LEGv8 processor, a Register File and an Arithmetic Logic Unit (ALU) along with a variety of other components must be incorporated within the processor and datapath. A detailed layout of the register file and a detailed design of an ALU were also established. All designs and complex layouts mentioned above were carefully constructed using the Altera Quartus II 15.0 (64-Bit) programmable logic device design software program.

• Provides an understanding of the design and function of ARM processors.

• Use of Quartus II 15.0 (64 Bit) software program

• 32 Bit ALU Design in accordance to desired instructions: AND, ORR, ADD, SUB LDUR (load) and STUR (store)

• Register File design (32 x 64-bit)

• Control Unit Design