sicajc Goto Github PK

plct-open-reports

PLCT实验室的公开演讲，或者决定公开的组内报告

programming_for_puzzled_notes

python_automation_examples

Automations_examples_from_FCC_online

readings-for-cs348k

This is a list of readings for CS348K.

recycle-bsv-lib

Collection of BSV packages.

risc-v

RISC-V CPU Core (RV32IM)

risc-v-cpu

A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.

rv32-verilog

A RV32 CPU and associated simulator implemented in System Verilog.

secure-aes

Verilog code for my paper that proposes a secure-AES algorithm with support for various FPGA boards.

sicajc

Config files for my GitHub profile.

simple_tpu

Basic TPU implementation

simplesoc

Very simple Cortex-M1 SoC design based on ARM DesignStart

simpletpu

A FPGA Based CNN accelerator, following Google's TPU V1.

soc-lab

大二下学期——计算机系统综合(SoC)——实验

soc_zynq

My SOC course notes taken from VIPIN

string_maching_engine

style-guides

lowRISC Style Guides

synopsys

Basic scripts for Synopsys Design Compiler and Synopsys IC Compiler

systolic-array-for-smith-waterman

This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times faster than a software running the same algorithm.

trainwreck_risc-v_processor

Original RISC-V 1.0 implementation. Not supported.

ventus-gpgpu

GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

veriloghdl-codes

Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.

vivado_design_flow

vlsi-dsp-review

vlsi_cad_project

My NCHU vlsi cad final project

vlsi_dsp_notes_hw_project

vlsi_lab

My introductory course in Digital VLSI design

xiangshan

Open-source high-performance RISC-V processor