shreesh-kulkarni / learn

Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.

RISC-V Resources

A community-driven compilation of RISC-V resources and learning material. The list is dynamically updated by the community and categorized based on different contexts of the RISC-V scope, taking also into account different levels of experience/knowledge, allowing anyone interested in RISC-V to discover RISC-V resources and relevant content (courses, software, documentation, articles etc.) in an organized fashion. Feel free to navigate through the resources listed below with their descriptions.

RISC-V is an open standard Instruction Set Architecture (ISA) based on established Reduced Instruction Set Computer (RISC) principles.

👋 Want to learn about RISC-V? Check out the Beginner-Level and Intermediate-Level Learning Pathways.

Table of Contents

• RISC-V Resources
  • Table of Contents
  • ➕ Making Contributions
  • 📙 Resources
    • Learning Pathways for RISC-V
      • Beginner
      • Intermediate
    • Relevant Documentation from RISC-V International
    • Articles and presentations

➕ Making Contributions

We love contributions! Thank you for your interest in contributing to our compilation of tutorial resources for RISC-V.

Contributing is easy, here are some steps to help get you started:

✔ Browse through the list of beginner and intermediate-level resources here to see if your resource is already included.

✔ If not, go to Issues, click on New issue and select the template for adding a new RISC-V tutorial resource.

✔ Enter the resource information in the fields provided and click Submit new issue.

✔ If you have a different contribution, you can select the General Request issue template from the provided issue types.

✔ You could also engage with an already open issue.

We may interact with you before adding your contributions.

📙 Resources

Learning Pathways for RISC-V

Beginner

For those with little or no knowledge of digital logic design. After studying the Digital Design book in this section, you could take the RVfpga course in the Intermediate section if you wish as it expands on concepts discussed in the book.

Resource	Author(s)	Description	Access
Digital Design and Computer Architecture RISC-V edition	Sarah L. Harris, David M. Harris	Covers the foundational knowledge of digital logic design and segues smoothly into RISC-V Processor implementation. Topics covered here include : Number systems and digital representation, Semiconductors and transistors, Logic Gates and Digital Design, C Programming, RISC-V Architecture, RISC-V Assembly, Memory systems, Embedded I/O systems	[Amazon book link]
Nand2Tetris (optional)	Noam Nisan, Shimon Schocken	A free hands-on tutorial on building a general-purpose computer from logic gates using a hardware simulator. Taking this course is optional.	[webpage]
learn-FPGA episode I: from blinky to RISC-V	BrunoLevy	A beginner's introduction to digital design of a RISC-V softcore on FPGAs. Episode I gently starts from a very basic blinker in VERILOG and morphs it step by step into a basic yet fully functional RISC-V SOC. It is also explained how to write programs in C and assembly for the SOC. (Required background: Basic knowledge of VERILOG)	[GitHub]

Intermediate

For those with some background in digital logic design.

Resource	Author(s)	Description	Access
Computer Organization and Design RISC-V edition: The Hardware Software Interface (2nd edition)	David A. Patterson, John L. Hennesy	Covers the RISC-V Instruction Set in general and does an in-depth examination of the core RISC-V instructions. It also does a deep dive into RISC-V processor implementations. Each chapter includes real-world applications by tying concepts discussed with available modern computers. The book also highlights the interactions between hardware and software by continuously optimizing a sample software program based on the new hardware concepts introduced in each chapter.	[Amazon book link]
Computer Architecture with an Industrial RISC-V Core [RVfpga]	Sarah Harris, Daniel Chaver-Martinez	This free EdX course expands on topics covered in Digital Design and Computer Architecture, RISC-V edition with hands-on learning. This course shows how to target a commercial RISC-V Core and RISC-V system-on-chip (SoC) to FPGA, program the RISC-V SoC, and add more functionalities to the RISC-V SoC	[Edx course link]
learn-FPGA episode II: pipelining	BrunoLevy	This tutorial explains how to transform the basic softcore from episode I into an efficient pipelined processor. The tutorial follows a step-by-step approach, starting from a 5-states processor, transforming the states into stages, and solving data and control hazards by first observing what happens in real programs thanks to the included debugger/disassembler. Then it is explained how to gain more performance using register forwarding. Finally, branch prediction is introduced, from the simplest static branch prediction to more elaborate ones (gshare). The effect of the different optimizations are demonstrated using different codes (the classical dhrystones and coremark benchmarks, and a program that computes an image using raytracing). (Required background: It is highly recommended to read episode I before episode II !)	[GitHub]

Relevant Documentation from RISC-V International

Resource	Description	Access
Member Benefits and Welcome deck	A set of slides useful for new RISC-V members to familiarize themselves with the scope/organization of the RISC-V community and learn about membership benefits, as well as how to integrate into the community as a member.	[Google Doc]
Getting Started Guide for RISC-V Members	This document is intended to give a member’s overview of the RISC-V technical organizations. The intended audience is both for new members as well as a reference for existing members.	[Google Doc]
RISC-V Technical Wiki	This page serves as the main anchor point for the most important pieces of technical information for RISC-V. If you're looking for something technical, start here.	[webpage]
RISC-V Lifecycle Guide	This document has been created to facilitate RISC-V member participation in the key activities involved in creating and running groups, writing of specifications, and contributing open-source software in support of RISC-V architectures. It is a guide, not the rules.	[Google Doc]
RISC-V Repository Map	A central point that directs to different repositories relevant to the RISC-V ecosystem. It includes the technical and non-technical, ISA and non-ISA related, software related, as well as collaboration related repositories for RISC-V available on Github.	[webpage]

Articles and presentations

Resource	Author(s)	Description	Access
Design of the RISC-V Instruction Set Architecture	Andrew Waterman	Andrew Waterman’s Doctorate of Philosophy dissertation in the University of California, Berkeley, about the RISC-V ISA. It covers how RISC-V is a well structured small base ISA with a variety of optional extensions, making RISC-V convenient for a range of purposes from research and education, low-power embedded devices, to more general-purpose, high-performance computing, with the existence of these optional extensions. It provides a comparison of RISC-V to other popular ISAs as well.	[pdf]
Past, Present and Future of RISC-V	Krste Asanović		[YouTube video]
Is RISC-V the Future	Roddy Urquhart		[webpage]