shahriar-0 / digital-logic-design-lab-experiments-s2023

Verilog implementation of different concepts in Digital Logic Design such as OTHFSM, AFG and Accelerators

Digital Logic Design Lab Experiments

Experiments of the digital logic design laboratory course at university of Tehran

• Digital Logic Design Lab Experiments
  • 1: Clock and Periodic Signal Generation
  • 2: Sequential Synthesis and FPGA Programming
  • 3: Function Generator
  • 4: Accelerator and Wrappers

1: Clock and Periodic Signal Generation

The goal of this experiment is to introduce the concepts of static characteristics of digital logic gates, delay times, clock frequency generation and digital system using schematic diagram and Verilog HDL.

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2: Sequential Synthesis and FPGA Programming

The first goal of this experiment is to introduce the concepts of state machines that are mostly used for controllers. The second goal is to get familiar with FPGA devices and implementation.

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3: Function Generator

The goal of this experiment is to design an Arbitrary Generator that is capable of generating a wide variety of waveforms with different amplitude and frequency. Among them are sine, square, rhomboid, saw-tooth and any arbitrary waveform.

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4: Accelerator and Wrappers

The goal of this experiment is to get familiar with concepts of SoC and Accelerator and how we can use them to reduce the CPU time.

digital-logic-design-lab-experiments-s2023's Issues

add OTHFSM module pic

in report file there is no picture of OTHFSM module