Does anyone remember why aarch64 code doesn't define memory region "type": "Normal memory, cacheable, write-through" in MAIR_EL1 ?
/*
* Memory types are defined in Memory Attribute Indirection Register.
* - nGnRnE Device non-Gathering, non-Reordering, No Early write acknowledgement
* - nGnRE Unused Device non-Gathering, non-Reordering, Early write acknowledgement
* - GRE Unused Device Gathering, Reordering, Early write acknowledgement
* - NORMAL_NC Normal Memory, Inner/Outer non-cacheable
* - NORMAL Normal Memory, Inner/Outer Write-back non-transient, Write-allocate, Read-allocate
* Note: These should match with contents of MAIR_EL1 register!
*/
enum mair_types {
DEVICE_nGnRnE = 0,
DEVICE_nGnRE = 1,
DEVICE_GRE = 2,
NORMAL_NC = 3,
NORMAL = 4
};