rusching / cs145-sjtu-labs

This reposity contains the labs of Computer Architecture, CS145 in SJTU.

CS145-SJTU-Labs

This reposity contains the labs of Computer Architecture, CS145 in SJTU.

There are 6 labs in this reposity. The ultimate goal of the project is to design a MIPS-like multicycle processor. The difficulty of the 6 labs is gradually increasing.

Contents

• Lab1: LED Flow Water Light

• Lab2: 4-bitAdder

• Lab3: Simple MIPS-like single-cycle processor component implementation-Ctr, ALU, ALUCtr

• Lab4: Simple MIPS-like single-cycle processor component implementation-Registers, Memory, Sign-extension

• Lab5: Design and implementation of MIPS-like single cycle processor

• Lab6: Design and implementation of MIPS-like multicycle pipelined processor

Run

The programming language is Verilog and the running environment is Vivado2018.3.

Notes

Those interested in MIPS-like processor architecture are welcome to refer to this project, and those taking CS145, SJTU are welcome to refer to this implementation as a reference, but do not copy it directly. Please finish your homework by yourself.