Comments (2)
rtwfroody
commented on August 12, 2024
1
I think you are right. I'll make a PR.
from riscv-debug-spec.
en-sc
commented on August 12, 2024
AFAIU, this can be fixed by modifying algorithm (1) by adding tow steps in the beginning:
- Write
tdata1=0(to be able to writetdata2) - Write
tdata2=0(AFAIU, zero is always valid for NAPOT match, regardless ofmaskmax6)
from riscv-debug-spec.
Related Issues (20)
- Typo/mistake in "Debug Mode" section/mprven HOT 1
- Clarification of register needed HOT 1
- Does *stateen0[57] control mscontext if implemented? HOT 2
- Timing requirements for a chain of `mcontrol` load address triggers HOT 2
- `mcontrol' / 'mcontrol6` `match=lt` trigger on the last valid address HOT 6
- A typo in [5.4. Native Triggers] HOT 1
- How to halt or resume multiple harts simultaneously? HOT 4
- Stored value availability to TM in case of AMOs HOT 6
- Hit bit interaction with action conflict when several triggers of the same priority match HOT 3
- How to reset the DM on the first connection on both 0.13 and 1.0 spec versions HOT 7
- Cross Trigger definition in RISC-V HOT 3
- Trigger match on csrrs/csrrc to tdata1 HOT 13
- Why debugger lose control of the hart while executing a program not terminate with an ebreak instruction
- Ambiguous requirement about dmcontrol behavior when dmcontrol.dmactive==0 HOT 2
- Register bit-field bit offset numbers clipped HOT 2
- Table cell justification/alignment issues HOT 1
- Typo on the minimum requirements of Debug Mode HOT 4
- Q about Table 9 (action encoding) HOT 8
- NAPOT matching HOT 2
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