SROW/SLOW shift masking about riscv-bitmanip

[eroom1966]

I think I may have answered my own question but would like it confirmed
in the case of the above instructions the shift mask is actually (32 - 1) which is the XLEN of the target register, not the XLEN of the machine (64 - 1)
Thx
Lee

[cliffordwolf]

The spec doesn't contain any pseudo-code for SROW, but in general, the RV64 *W instructions implement the same semantics as the regular non-W version of the instruction on RV32. I.e. yes, the shift mask for SROW is 31, just like the shift mask for the base ISA SLLW, SRLW, and SRAW instructions.