eroom1966 Goto Github PK

core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

cvw

Configurable RISC-V Processor

dump1090

Dump1090 is a simple Mode S decoder for RTLSDR devices

esp32-i2c-master

this example file implements a esp32 as master that can communicate with another esp32 (as slave)

esp32-i2c-slave

this example file implements a esp32 as slave that can communicate with another esp32 (as master)

esp32-softap-ota

Minimal esp-idf example of HTTP portal to perform OTA updates of ESP32 in SoftAP mode

frogfs

Fast Read-Only General-purpose File System (ESP32/ESP8266 compatible)

ibex

Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

ogn-aprs-protocol

ogn-rf

This software listens to OGN radio messages and sends it to Open Glider Network.

riscv-bitmanip

Working draft of the proposed RISC-V Bitmanipulation extension

riscv-compliance

riscv-dv

SV/UVM based instruction generator for RISC-V processor verification

riscv-dv.top

riscv-ovpsim

OVP Simulator for RISC-V

riscv-spike

riscv-toolchains

gnu toolchains including vector assembler

riscv-toolchains-rvv-0.8.x

riscv-v-spec

Working draft of the proposed RISC-V V vector extension

rvvi

RISC-V Verification Interface

stratux

Fork of the original cyoung/stratux with multiple patches for flying in europe

toolchains

ttgo-t4-demo