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Async clks in rvvi_vlg about rvvi HOT 3 CLOSED

MikeCovrado avatar MikeCovrado commented on August 21, 2024
Async clks in rvvi_vlg

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Comments (3)

eroom1966 avatar eroom1966 commented on August 21, 2024

@MikeCovrado
I think this may no longer be a requirement, I am going to back this out and run some tests

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eroom1966 avatar eroom1966 commented on August 21, 2024

We must have one shifted clock - otherwise we process the output on the RVVI interface one cycle too late.
If there is an alternative to this, I am interested in hearing the approach.

I wonder, are we thinking it is OK to maintain one-cycle latency so that reports in ImperasDV are delayed from when they actually occur ?

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Imperas avatar Imperas commented on August 21, 2024

The current version of RVVI-TRACE specification now only has one clock. [Simon]

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