rigetti / admittancemodels.jl

Analysis of linear systems using admittance models

AdmittanceModels.jl

AdmittanceModels.jl is a package for creating and manipulating linear input-output models of the form YΦ = Px, y = QᵀΦ where x are the inputs and y are the outputs. One example of such a model is a Positive Second Order model, defined in [1]. Such models can capture the equations of motion of a circuit consisting of inductors, capacitors, and resistors.

The scripts in paper were used to generate the figures in [1].

If you use this package in a publication, please cite our paper:

@article{ScheerBlock2018,
    author = {Michael G. Scheer and Maxwell B. Block},
    title = "{Computational modeling of decay and hybridization in superconducting circuits}",
    year = "2018",
    month = "Oct",
    note = {arXiv:1810.11510},
    archivePrefix = {arXiv},
    eprint = {1810.11510},
    primaryClass = {quant-ph},
}

[1] Computational modeling of decay and hybridization in superconducting circuits

Installation

Clone the repository from GitHub and install Julia 1.1. No build is required beyond the default Julia compilation.

Example usage: the circuit in Appendix A of [1]

Construct the circuit in Appendix A, with arbitrarily chosen values.

using AdmittanceModels
vertices = collect(0:4)
circuit = Circuit(vertices)
set_capacitance!(circuit, 0, 1, 10.0)
set_capacitance!(circuit, 1, 2, 4.0)
set_capacitance!(circuit, 0, 3, 4.0)
set_capacitance!(circuit, 2, 3, 5.0)
set_capacitance!(circuit, 3, 4, 5.0)
set_inv_inductance!(circuit, 1, 2, 3.5)
set_inv_inductance!(circuit, 0, 3, 4.5)

Use the spanning tree in Appendix A to find a Positive Second Order model.

root = 0
edges = [(1, 0),
         (3, 0),
         (4, 0),
         (2, 1)]
tree = SpanningTree(root, edges)
PSOModel(circuit, [(4, 0)], ["port"], tree)

The tree is optional because a change of spanning tree is simply an invertible change of coordinates.

PSOModel(circuit, [(4, 0)], ["port"])

Example usage: a λ/4 transmission line resonator capacitively coupled to a transmission line

The model we will analyze is similar the device shown below, from Manufacturing low dissipation superconducting quantum processors.

Create CircuitComponent objects for the model.

using AdmittanceModels
ν = 1.2e8 # propagation_speed
Z0 = 50.0 # characteristic_impedance
δ = 100e-6 # discretization length

resonator = TransmissionLine(["coupler_0", "short"], ν, Z0, 5e-3, δ=δ)
tline = TransmissionLine(["in", "coupler_1", "out"], ν, Z0, 2e-3, locations=[1e-3], δ=δ)
coupler = SeriesComponent("coupler_0", "coupler_1", 0, 0, 10e-15)
components = [resonator, tline, coupler]

Use PSOModel objects to compute the frequency and decay rate of quarter wave resonator mode. Include resistors at the ports in order to get the correct decay rate.

resistors = [ParallelComponent(name, 0, 1/Z0, 0) for name in ["in", "out"]]
pso = connect(PSOModel.([components; resistors]))
pso = short_ports(pso, "short")
λs, _ = lossy_modes_dense(pso, min_freq=3e9, max_freq=7e9)
freq = imag(λs[1])/(2π)
decay = -2*real(λs[1])/(2π)

Compute the transmission scattering parameters Blackbox. This uses a closed form representation of the transmission lines.

ω = collect(range(freq - 2 * decay, stop=freq + 2 * decay, length=300)) * 2π
bbox = connect(Blackbox.(Ref(ω), components))
bbox = short_ports(bbox, "short")
bbox = open_ports_except(bbox, ["in", "out"])
S = [x[1,2] for x in scattering_matrices(bbox, [Z0, Z0])]

Plot the magnitude of the scattering parameters.

using PlotlyJS
plot(scatter(x=ω/(2π*1e9), y=abs.(S)), Layout(xaxis_title="Frequency [GHz]", yaxis_title="|S|"))

Plot the phase of the scattering parameters.

plot(scatter(x=ω/(2π*1e9), y=angle.(S)), Layout(xaxis_title="Frequency [GHz]", yaxis_title="Phase(S)"))

Using with ANSYS Q3D Extractor

Plain text files containing RLGC parameters exported by ANSYS® Q3D Extractor® software can be used to construct a Circuit object via Circuit(file_path). Currently only capacitance matrices are supported.

ANSYS and Q3D Extractor are registered trademarks of ANSYS, Inc. or its subsidiaries in the United States or other countries.

admittancemodels.jl's Issues

Add benchmarks

... using PkgBenchmark.jl.

Input and output port matrices

I'm not sure why input and output port matrices are allowed to differ for both Blackbox and PSOModel if there is only one vector of port names. Perhaps am I missing some obvious reason to do this?

API style consistency

The arguments of set_inductance!(c::Circuit, v0, v1, value) and related methods have an unfortunate ordering. Consider that for arrays, the syntax A[inds...] = X is lowered to setindex!(A, X, inds...), i.e. the set value precedes the indices.

Register in General

I think the bot is now added so we can do this: @JuliaRegistrator register()

graceful exit when there is no capacitance associated with a node

When C matrix has zero rows (such as when user accidentally defines resistive elements to disconnected ports) This matrix is not invertible. And in return julia returns a singularity error. Diagonal entries of this matrix (C should have a non zero diagonal if am I not mistaken) can be checked and user can be warned here.

AdmittanceModels.jl/src/pso_model.jl

Line 89 in 7b235d5

M = collect([C Z; Z I]) \ collect([-G -K; I Z])

Port type parameter for circuit components

In src/circuit_components.jl, ports are assumed to be identified by Strings, but this not enforced elsewhere in the package. Probably the circuit components should have a type parameter for the port names.

See also #22; potentially one carefully thought out PR could address both issues.

Port types?

In discussing #11, Michael wrote:

After some thought, I agree that Cascade is not really necessary and given that things are generally more readable without it I'm in favor of making this change. I do like being able to specify what happens to the ports ahead of time though, as this would avoid some repeated code in the code for the paper. So if you have ideas for a better way to do that, that would be cool, though it's not that important.

To accomplish such functionality, it seems like a Port type would be necessary.

Model equality

AdmittanceModels are not considered equal if columns of the input/output port matrices are permuted, with port names correspondingly permuted. I think it should be safe to consider such models equal---the ordering is entirely arbitrary and not even tied to gauge choice. Columns of the port matrix are not indexed directly, rather only after looking up the column index using the port names vector. Likewise, I think Circuits should be considered equal if equal up to a permutation of the vertices.

Furthermore, I noticed there is an isapprox method defined for AdmittanceModels. It appears convenient for some tests but I am not sure how correct it is to implement this because the atol and rtol flags are inaccessible. atol and rtol would be most useful if they were able to be specified for each matrix separately in the case of a PSOModel (or Circuit, which is not an AdmittanceModel but has a method similarly defined). As implemented, the method does not work in general, because isapprox is not defined for arrays of String port names, for example. Finally, I think there is a sense in which one could speak of different kinds of models approximating each other but that's not allowed here.

AdmittanceModels.jl/src/admittance_model.jl

Lines 87 to 102 in f100752

	function Base. ==(am1::AdmittanceModel, am2::AdmittanceModel)
	t = typeof(am1)
	if typeof(am2) != t
	return false
	end
	return all([getfield(am1, name) == getfield(am2, name) for name in fieldnames(t)])
	end
	function Base.isapprox(am1::AdmittanceModel, am2::AdmittanceModel)
	t = typeof(am1)
	if typeof(am2) != t
	return false
	end
	return all([getfield(am1, name) ≈ getfield(am2, name) for name in fieldnames(t)])
	end

`cascade_and_unite` deserves an easier name to type

The name is good in that the functionality is self-evident if you have read the paper, but for such a common operation it is a drag to type that many characters.

I suggest connect to indicate that the operation amounts to connecting multiple admittance models (or circuits) at their shared ports.