rggen / rggen-sample-testbench Goto Github PK

Hello,

If a register implements fewer bits than the bus width, then some portion of input signals, i_bit_field_value and i_bit_filed_read_data, to rggen_default_register are HiZs.

To avoid this, could rggen be updated to pass the correct width(sum of bit_field widths) to DATA_WIDTH parameter instead if setting that parameter to BUS_WIDTH? Would that have any other side effects and cause functional issues?

https://www.metrics.ca/product

I use VCS to run this testbench.
I use command : make , in directory "rggen-sample-testbench-master/sim/apb/verilog"

But I have error as following:

make sim_vcs TEST=ral_hw_reset_test
make[1]: Entering directory '/home/jamesning/work/reggen/rggen-sample-testbench-master/sim/apb/verilog'
[ -f simv ] || make compile_vcs
make[2]: Entering directory '/home/jamesning/work/reggen/rggen-sample-testbench-master/sim/apb/verilog'
vlogan -full64 -sverilog -timescale=1ns/1ps -ntb_opts uvm-1.2 -l vlogan_uvm.log

Warning-[MXIR-W] VCS-MX build is required
Please make sure that vlogan is from the intended build.

                     Chronologic VCS (TM)
   Version O-2018.09-SP2_Full64 -- Thu Aug 24 13:32:38 2023
           Copyright (c) 1991-2018 by Synopsys Inc.
                     ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Error-[ILWOR] Incorrect Logical Worklib or Reflib
The incorrect logical lib is "work".
Please check your Synopsys setup file.

CPU time: .110 seconds to compile
make[2]: *** [/home/jamesning/work/reggen/rggen-sample-testbench-master/sim/vcs.mk:69: compile_vcs] Error 255
make[2]: Leaving directory '/home/jamesning/work/reggen/rggen-sample-testbench-master/sim/apb/verilog'
make[1]: *** [/home/jamesning/work/reggen/rggen-sample-testbench-master/sim/vcs.mk:64: sim_vcs] Error 2
make[1]: Leaving directory '/home/jamesning/work/reggen/rggen-sample-testbench-master/sim/apb/verilog'
make: *** [makefile:32: ral_hw_reset_test] Error 2

Would you please help me to fix the bug?

Hi,
I'm using the rggen generated models for our design and verification.

And I'm using AXI interface, for which I'm using AXI VIP for verification. when I'm trying to start uvm_reg_access_seq I'm getting the following error.

the corresponding line is:

Please help me in solving this issue..

Thanks.

Regards,
Tejoyadav

Hi，
After fix some error， I still have this error when I run make in direction rggen-sample-testbench/sim/apb/verilog :

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Parsing design file '/usr/synopsys/vcs2018.09/vcs/O-2018.09-SP2/etc/uvm-1.2/uvm_pkg.sv'
Parsing included file '/usr/synopsys/vcs2018.09/vcs/O-2018.09-SP2/etc/uvm-1.2/uvm_macros.svh'.
Parsing included file '/usr/synopsys/vcs2018.09/vcs/O-2018.09-SP2/etc/uvm-1.2/macros/uvm_version_defines.svh'.
Back to file '/usr/synopsys/vcs2018.09/vcs/O-2018.09-SP2/etc/uvm-1.2/uvm_macros.svh'.
Parsing included file '/usr/synopsys/vcs2018.09/vcs/O-2018.09-SP2/etc/uvm-1.2/macros/uvm_global_defines.svh'.
Back to file '/usr/synopsys/vcs2018.09/vcs/O-2018.09-SP2/etc/uvm-1.2/uvm_macros.svh'.
Parsing included file '/usr/synopsys/vcs2018.09/vcs/O-2018.09-SP2/etc/uvm-1.2/macros/uvm_message_defines.svh'.
Back to file '/usr/synopsys/vcs2018.09/vcs/O-2018.09-SP2/etc/uvm-1.2/uvm_macros.svh'.
Parsing included file '/usr/synopsys/vcs2018.09/vcs/O-2018.09-SP2/etc/uvm-1.2/macros/uvm_phase_defines.svh'.
Back to file '/usr/synopsys/vcs2018.09/vcs/O-2018.09-SP2/etc/uvm-1.2/uvm_macros.svh'.
Parsing included file '/usr/synopsys/vcs2018.09/vcs/O-2018.09-SP2/etc/uvm-1.2/macros/uvm_object_defines.svh'.
Back to file '/usr/synopsys/vcs2018.09/vcs/O-2018.09-SP2/etc/uvm-1.2/uvm_macros.svh'.
Parsing included file '/usr/synopsys/vcs2018.09/vcs/O-2018.09-SP2/etc/uvm-1.2/macros/uvm_printer_defines.svh'.
Back to file '/usr/synopsys/vcs2018.09/vcs/O-2018.09-SP2/etc/uvm-1.2/uvm_macros.svh'.
Parsing included file '/usr/synopsys/vcs2018.09/vcs/O-2018.09-SP2/etc/uvm-1.2/macros/uvm_tlm_defines.svh'.
Parsing included file '/usr/synopsys/vcs2018.09/vcs/O-2018.09-SP2/etc/uvm-1.2/tlm1/uvm_tlm_imps.svh'.
Back to file '/usr/synopsys/vcs2018.09/vcs/O-2018.09-SP2/etc/uvm-1.2/macros/uvm_tlm_defines.svh'.
Back to file '/usr/synopsys/vcs2018.09/vcs/O-2018.09-SP2/etc/uvm-1.2/uvm_macros.svh'.
Parsing included file '/usr/synopsys/vcs2018.09/vcs/O-2018.09-SP2/etc/uvm-1.2/macros/uvm_sequence_defines.svh'.
Back to file '/usr/synopsys/vcs2018.09/vcs/O-2018.09-SP2/etc/uvm-1.2/uvm_macros.svh'.
Parsing included file '/usr/synopsys/vcs2018.09/vcs/O-2018.09-SP2/etc/uvm-1.2/macros/uvm_callback_defines.svh'.
Back to file '/usr/synopsys/vcs2018.09/vcs/O-2018.09-SP2/etc/uvm-1.2/uvm_macros.svh'.
Parsing included file '/usr/synopsys/vcs2018.09/vcs/O-2018.09-SP2/etc/uvm-1.2/macros/uvm_reg_defines.svh'.
Back to file '/usr/synopsys/vcs2018.09/vcs/O-2018.09-SP2/etc/uvm-1.2/uvm_macros.svh'.
Parsing included file '/usr/synopsys/vcs2018.09/vcs/O-2018.09-SP2/etc/uvm-1.2/macros/uvm_deprecated_defines.svh'.
Back to file '/usr/synopsys/vcs2018.09/vcs/O-2018.09-SP2/etc/uvm-1.2/uvm_macros.svh'.
Back to file '/usr/synopsys/vcs2018.09/vcs/O-2018.09-SP2/etc/uvm-1.2/uvm_pkg.sv'.

Error-[SE] Syntax error
Following verilog source has syntax error :
"/usr/synopsys/vcs2018.09/vcs/O-2018.09-SP2/etc/uvm-1.2/uvm_pkg.sv", 32:
token is ';'
package uvm_pkg;
^

1 error
CPU time: .161 seconds to compile
make[2]: *** [/home/jamesning/work/reggen/rggen-sample-testbench/sim/vcs.mk:74: compile_vcs] Error 255
make[2]: Leaving directory '/home/jamesning/work/reggen/rggen-sample-testbench/sim/apb/verilog'
make[1]: *** [/home/jamesning/work/reggen/rggen-sample-testbench/sim/vcs.mk:64: sim_vcs] Error 2
make[1]: Leaving directory '/home/jamesning/work/reggen/rggen-sample-testbench/sim/apb/verilog'
make: *** [makefile:31: ral_hw_reset_test] Error 2

Would you please tell me how to solve it? Thank you

the error message:

CPU time: .989 seconds to compile
make dut.f
make[3]: Entering directory /home/kevin/work/rggen/rggen-sample-testbench/sim/apb/verilog' flgen --output=dut.f --define-macro=RGGEN_VERILOG --define-macro=RGGEN_ENABLE_SVA --define-macro=RGGEN_ENABLE_BACKDOOR --define-macro=RGGEN_ENABLE_ENHANCED_RAL /home/kevin/work/rggen/rggen-sample-testbench/rtl/compile.rb no such file or directory -- rggen-verilog-rtl/compile.rb @/home/kevin/work/rggen/rggen-sample-testbench/rtl/compile.rb:7 make[3]: *** [dut.f] Error 1 make[3]: Leaving directory /home/kevin/work/rggen/rggen-sample-testbench/sim/apb/verilog'
make[2]: *** [compile_vcs] Error 2
make[2]: Leaving directory /home/kevin/work/rggen/rggen-sample-testbench/sim/apb/verilog' make[1]: *** [sim_vcs] Error 2 make[1]: Leaving directory /home/kevin/work/rggen/rggen-sample-testbench/sim/apb/verilog'
make: *** [ral_hw_reset_test] Error 2

Hi, I appreciated what you did!
I am trying the sample tb but I cannot find the files poped in terminal. I saw the folders and files located in the root folder of the sample tb repo. I don't know why it poped error.

case ENV['LANGUAGE']
when 'systemverilog'
file_list 'rggen-sv-rtl/compile.rb', from: :current
source_file "#{ENV['PROTOCOL']}/block_0.sv"
source_file "#{ENV['PROTOCOL']}/block_1.sv"
when 'verilog'
file_list 'rggen-verilog-rtl/compile.rb', from: :current
source_file "#{ENV['PROTOCOL']}/block_0.v"
source_file "#{ENV['PROTOCOL']}/block_1.v"
when 'vhdl'
file_list 'rggen-vhdl-rtl/compile.rb', from: :current
source_file "#{ENV['PROTOCOL']}/block_0.vhd"
source_file "#{ENV['PROTOCOL']}/block_1.vhd"
end

this is the file who will find the needed things.

I am not familiar with ruby, please help!