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arm_m3_design

personal practice

avnet_hdl

basic_verilog

Must-have verilog systemverilog modules

caravel

Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.

cmos_vlsi_design

COMS 超大规模集成电路设计书籍

communications_system

通信系统类书籍(无线通信，数字通信，信号系统，通信原理等)

core_ddr3_controller

A DDR3 memory controller in Verilog for various FPGAs

daisho

SuperSpeed USB 3.0 FPGA platform

darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

ddr4_controller

e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

ethernet

Verilog Ethernet components for FPGA implementation

fpga

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

fpga-ftdi245fifo

FPGA-based USB fast communication using FT232H/FT600 chip.

hdl

HDL libraries and projects

hdl-bits-solutions

This is a repository containing solutions to the problem statements given in HDL Bits website.

hdlconvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTL4

hw

ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

integrated_circuits_and_semiconductor

Integrated_Circuits_and_Semiconductor 集成电路设计与半导体物理器件书籍

interesting-python

有趣的Python爬虫和Python数据分析小项目(Some interesting Python crawlers and data analysis projects)

luna

a USB multitool + Amaranth HDL framework for monitoring, hacking, and developing USB devices

main_mister

Main MiSTer binary and Wiki

nyuziprocessor-gpu

GPGPU microprocessor architecture

oh

Verilog library for ASIC and FPGA designers

open_free_list

Open FreeList

openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

or1k-gcc

GCC port for OpenRISC 1000

pci_e

PCI_Express总线经典书籍

pulp

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.