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soc_event_generator

softmc

SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. The design, the interface, and its capabilities and limitations are discussed in our HPCA 2017 paper: "SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies" <https://people.inf.ethz.ch/omutlu/pub/softMC_hpca17.pdf>

softmc-ddr4

source-routing-on-network-on-chip

spacevim

:two_hearts: A community-driven vim distribution inspired by spacemacs

sparrow-kata

Project Sparrow: KataOS

sparrow-manifest

Project Sparrow: Repo Materials

speculation-barrier

This project provides a header file which contains wrapper macros for the __builtin_load_no_speculate builtin function defined at https://www.arm.com/security-update This builtin function defines a speculation barrier, which can be used to limit the conditions under which a value which has been loaded can be used under speculative execution.

sphinx-verilog-domain

Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.

sphinx_f4pga_theme

A material-based, responsive theme inspired by mkdocs-material

sphinxcontrib-hdl-diagrams

Sphinx Extension which generates various types of diagrams from Verilog code.

static-analysis

⚙️ A curated list of static analysis (SAST) tools for all programming languages, config files, build tools, and more. The focus is on tools which improve code quality.

stats-schema

A proposal for a shared statistics schema

struct_mapping

Mapping json to and from a c++ structure

style-guides

lowRISC Style Guides

styleguide

Style guides for Google-originated open-source projects

surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

symbiyosys

SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows

symbolator

HDL symbol generator

synthesis-example

Example of a full DC synthesis script for a simple design

sysctest_qshan

systemc

SystemC - design and testbench examples

systemc-accellera

Core SystemC Library

systemc-common-practices

systemverilog

SystemVerilog examples and projects

systemverilog.vim

SystemVerilog vim scripts

systemverilogassertions

Examples and reference for System Verilog Assertions

systemverilogreference

training labs and examples

systemverilogsha256

SHA256 in (System-) Verilog / Open Source FPGA Miner