计算机组成原理课程实验:使用Verilog编写流水线CPU
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实现完全转发
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实现冒险检测
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实现36条指令
SLL SRL SRA SLLV SRLV SRAV JR MOVZ MOVN ADD ADDU SUB SUBU AND OR XOR NOR SLT SLTU BLTZ BGEZ J BEQ BNE BLEZ BGTZ ADDI ADDIU SLTI SLTIU ANDI ORI XORI LUI LW SW
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实现下载
具体见Readme.pdf
This project forked from lyncien/mips-v
组成原理课程实验:MIPS 流水线CPU,实现36条指令,转发,冒险检测
License: GNU General Public License v3.0
计算机组成原理课程实验:使用Verilog编写流水线CPU
实现完全转发
实现冒险检测
实现36条指令
SLL
SRL
SRA
SLLV
SRLV
SRAV
JR
MOVZ
MOVN
ADD
ADDU
SUB
SUBU
AND
OR
XOR
NOR
SLT
SLTU
BLTZ
BGEZ
J
BEQ
BNE
BLEZ
BGTZ
ADDI
ADDIU
SLTI
SLTIU
ANDI
ORI
XORI
LUI
LW
SW
实现下载
具体见Readme.pdf
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