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This is Amirkabir University Logic Circuit Design final project 2022
VHDL 19.27%
HTML 4.58%
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design-alu-with-xilinx-ise's Introduction
Design ALU with Xilinx ISE Design - Amirkabir University Logic Circuits Design Final Project
What you will learn by doing this project:
- Work with Xilinx ISE
- Basics of VHDL programing language
- Implementing a 4-bit Full Adder with VHDL
- Implementing a common base
- Implementing one 16-bit register
- Implementing Data path
- Implementing E filpflap
- Implementing ALU unite
- How To simulate a circuit
- Xilinx Design Tools 14.7 (Only Works on Windows 7,8,10)
Descriptions of the files of this project:
- Project.pdf
- In this file, all details about the project have been explained.
- Report_Part_1.docx
- Report file for the first part of the project. All results of implemented VHDL codes are visible here.
- Report_Part_2&3.docx
- Report file for the second and third parts of the project. All results of implemented VHDL codes are visible here.
- FullAdder
- Directory of Full Adder code (First Part of project).
- Mano_DataPath
- Directory of ALU and Mano path code (second and third parts of project)
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