The aim of our project is to design and test a simple single cycle RISC processor, and to build a data path ISA which has three instructions formats namely, R-type, I-type and J-type with 24-bits using the Logisim simulator tool.
osamarimawi / pipelined_risc_processor Goto Github PK
View Code? Open in Web Editor NEWdesigning a simple pipelined RISC processor with some specifications