os-fpga / yosys_verific_rs

Yosys + (Optional) Verific Integration

Introduction

This repository is designed for the Yosys + (Optional) Verific support. The open-source Yosys has extensive Verilog-2005 support while Verific adds complete support for SystemVerilog IEEE-1800, UPF IEEE-1801 and VHDL IEEE-1076 standards. The repository contains yosys_rs, and open-source HDL projects as submodules, which are going to be used for the Synthesis and Verification. It also contains Yosys template scripts which can be used in the OpenFPGA tasks for the yosys_vpr flow. These scripts are designed to be used only with Yosys with Verific enabled. Contact Verific directly to subscribe the optional Verific License. Contact [email protected] for support with the Verific integration in this repo.

Requirements

The list of dependencies:

• Ubuntu
• Centos
• MacOS

Repository Structure

.
|-- analyze
|-- RTL_Benchmark
|-- benchmarks
|-- logic_synthesis-rs
|-- scripts
|-- suites
|-- Raptor_Tools
|-- yosys
|-- yosys-plugins
`-- yosys-rs-plugin
    

The repository has the following submodules:

• yosys
• yosys-plugins
• yosys-rs-plugin
• Raptor_Tools
• logic_synthesis-rs
• RTL_Benchmark

The directory structure is the following:

• analyze directory contains analyze tool and it's unit tests.
• benchmarks directory contains benchmark open-source designs - SHOULD BE REMOVED:
  • verilog holds Verilog language desings.
  • mixed_languages holds mixed language desings.
  • vhdl holds VHDL submodule designs.
• suites directory contains benchmark suites which can be automatically run by the automation scripts available at scripts/synth.
• scripts directory contains automation scripts:
  • benchmarks holds Yosys synthesis scripts for the available benchmarks.
  • log_automation holds the automation scripts to extract metrics from tools output log files.
  • synth holds the automation scripts to run synthesis on different tools.
  • task_generator holds the OpenFPGA tasks generator script and it's default settings JSON file.
  • yosys_templates holds the OpenFPGA Yosys template scripts which are written to use the verific frontend.
• Raptor_Tools directory contains Raptor_Tools submodule which has Flex_LM library and verific_rs submodule.
• yosys directory contains Yosys submodule.
• yosys-plugins directory contains yosys-symbiflow-plugins submodule.
• yosys-rs-plugin directory contains yosys-rs-plugin submodule.
• logic_synthesis-rs directory contains logic_synthesis-rs submodule which has DE and abc_rs submodule.
• RTL_Benchmark directory contains RTL_Benchmark submodule.

Build

Run release Makefile target to build Yosys with Verific enabled:

make release

Provide PRODUCTION_BUILD=ON option to build in production mode:

make release PRODUCTION_BUILD=ON

Run install Makefile target to build and install Yosys with Verific enabled:

make install PREFIX=<INSTALL_DIR>

All available Makefile targets can be seen running help target:

make help

Note: If you would like to update your local repository and build, then run the following commands.

  cd yosys_verific_rs
  git pull
  make UPDATE_SUBMODULES=ON

Running tests

Initialize/update RTL_Benchmark submodule:

git submodule update --init --recursive --progress RTL_Benchmark

Execute python script to run suite of benchmarks:

python3 scripts/synth/synthesis.py --config_files suites/Golden/Golden_synth_rs_ade_with_bram_with_dsp.json

How to generate yosys+verific OpenFPGA tasks

To generate tasks with default configurations/settings the following command should be run:

python3 scripts/task_generator/run_task_generator.py PATH_TO_OPENFPGA_ROOT --debug

To generate tasks with specific configurations/settings the following command should be run:

python3 scripts/task_generator/run_task_generator.py PATH_TO_OPENFPGA_ROOT --settings_file SPECIFIC_SETTINGS.json --debug

Detailed information regarding OpenFPGA tasks generation can be found here.

yosys_verific_rs's Issues

QoR analysis for RTL_Benchmarks benchmarks compared with Vivado

Perform experiments by enabling/disabling different verific runtime flags to improve yosys QoR compared to Vivado. The experiments need to be done based on RTL_Benchmark benchmarks. The initial data is available in the attached Excel. The latest Yosys-v0.12 should be used for the experiments.
RTL_Benchmark_comparision_.xlsx

Generate new benchmarks using LiteX tool.

https://github.com/RapidSilicon/litex_ip_integration - RS version of LiteX with a custom IP support.
https://github.com/enjoy-digital/litex - open source LiteX.

Please use RS version.

After successfull generatio of benchmarks the following should be done:

• add the generated benchmarks to the repository.
• create JSON suite for those benchmarks
• perform synthesis for the suite on all available tools
• perform QoR analysis.

Add SystemVerilog language designs/tests

We should research and find open source designs which can be sythesized. The final target is to systhesize the design using yosys+verific and verify the results with the simulation. The initial experiments can be done using Vivado or Quartus till the yosys+verific flow and scripts are ready.

The extracted runtime values don't match with actual runtime

Currently benchmarks runtime is extracted from the run.log file, which seems that is not correctly representing the actual runtime. The correct runtime of a benchmark is available at the end of the yosys_output.log file (see picture below). It is the sum of abc (50 sec) and user (39.00s) seconds, so for the provided example it would be 89.00 seconds.

Correct submodule names

Currently paths are used as submodule names for the benchmarks, which is not correct. Also yosys_rs submodule name should be changedd to yosys

QoR analysis for QL benchmarks compared with Vivado.

Perform experiments by enabling/disabling different verific runtime flags to improve yosys QoR compared to Vivado. The experiments need to be done based on QL benchmarks. The baseline data is available in the attached Excel. The latest Yosys-v0.12 should be used for the experiments.
QL.xlsx

For each enabled/disabled Verific runtime flag the following information should be recorded։

• LUT percentage average gain/loss for all benchmarks
• LUT percentage max gain/loss for all benchmarks

Functionality to copy existing task for task generator script.

Currently there is no way to copy existing task without any modification.

QoR analysis for IWLS2005 benchmarks compared with Vivado

Perform experiments by enabling/disabling different verific runtime flags to improve yosys QoR compared to Vivado. The experiments need to be done based on IWLS2005 benchmarks. The initial data is available in the attached Excel. The latest Yosys-v0.12 should be used for the experiments.
Initial_results_IWLS2005.xlsx

Add yosys+verific template synthesis scripts

Add the yosys+verific template synthesis scripts which are available at OpenFPGA_RS/pull/16

Create scheduled Github actions to run weekly tests

The Github action should run scripts/synth/synthesis.py scirpt for the following suites:

• ?
• ?

After execution of the scripts/synth/synthesis.py scirpt the scripts/log_automation/run_metrics_extractor.py metrics extraction script should be run on the results.

Add percentage columns for MAX_LOGIC_LEVEL and AVERAGE_LOGIC_LEVEL metrics

Add functionality to specify custom settings for an individual benchmark

Currently in JSON settings file of the synthesis.py we specify general settings for all benchmarks. This task is for enhancing the functionality to be able to specify custom settings for an individual benchmark - so if custom setting is specified then it should override the general setting, otherwise the general setting should be used.

Create Quartus and Diamond synthesis scripts

We need to create synthesis TCL scripts for Quartus and Diamond. We need to find LUT6 based architectures for Quartus and Diamond that we can use in the syntesis script.

Integrate and validate enhancement of Yosys-Verific Patch

Aram,

can you pick up the patch based on instructions on [email protected], integrate it, recompile yosys-verific with it and validate it ?

Please check if it fixes the 4 or 5 failing verific-related tasks that you currently have in your tasks suite.

If everything is fine please commit the new Yosys source code and let us know.

Thanks

Setup CI for the RapidSilicon/yosys_verific_rs repository.

The CI should perform the following steps sequentially:

• checkout the repository
• build yosys+verific (may be limitation from Verific license - should be checked)
• checkout OpenFPGA_RS
• build OpenFPGA_RS
• set yosys path ot yosys+verific
• run test generation script
• run yosys+verific regression tests.

Add mixed language designs/tests

We should research and find open source designs which can be sythesized. The final target is to systhesize the design using yosys+verific and verify the results with the simulation. The initial experiments can be done using Vivado or Quartus till the yosys+verific flow and scripts are ready.

Update Readme of the OpenFPGA task generator script.

The latest enhancements of the generator related to the discard_config_sections and ${ROOT_PATH} are not present in the README. Please add appropriate information there.

Add VHDL language designs/tests

We should research and find open source designs which can be sythesized. The final target is to systhesize the design using yosys+verific and verify the results with the simulation. The initial experiments can be done using Vivado or Quartus till the yosys+verific flow and scripts are ready.

Add CI for unit tests

Add a continuous integration workflow which will run unit tests (build yosys_verific_rs and run yosys-rs-plugin unit tests). This workflow will be triggered on every pull request of the following repositories:

• yosys-rs
• yosys-rs-plugin
• abc-rs
• yosys_verific_rs

QL benchmark CH_DFSIN too long rantime on yosys+verific

We should investigate and find the cause of long runtime.

Simple automation script to run synthesis with different synthesis scripts on all benchmarks.

There is a need to create a simple script which will automate experiments for the Synthesis.
The following functionality and requirements should be implemented:

• The script should be written for Python 3
• It should take as input JSON configuration file with the following format

{
  "yosys_path": "PATH_TO_THE_YOSYS_EXECUTABLE",
  "abc_path": "PATH_TO_THE_ABC_EXECUTABLE",
  "yosys_template_script": "THE_YOSYS_TEMPLATE_SCRIPT",
  "verific": true/false,
  "benchmarks": [
    {
      "name": "BENCHMARK_NAME"
      "rtl_path": "PATH_TO_RTL_FOLDER",
      "top_module": "TOP_MODULE_NAME"
    },
    ...
  ]
}

• all Yosys template and custom ABC scripts should be in the scripts/synth directory.
• the Yosys template scripts may contain the following variables which will be substituted by real Yosys commands/names within the automation script:
  • ${READ_HDL} - will be substituted by read -verific/noverific followed by read -sv/vhdl RTL_FILES
  • ${TOP_MODULE} - will be substituted by top module name
  • ${BENCHMARK_NAME} - will be substituted by benchmark name
• The script should create new output folder for each run: results_DATE_TIME
• The script should create the following output files in the output folder:
  • BENCHMARK_NAME.out - yosys console output
  • BENCHMARK_NAME.v - synthesized output Verilog
• The automation script should read the input JSON file and for each benchmark listed in "benchmarks" create Yosys script from the provided "yosys_template_script" and execute Yosys with the newly created Yosys script.

The following custom ABC scripts provided by Thierry are located in Khyber server under /tmp directory

• abc4.scr
• abc6.scr
• abc7.scr

The simple and starting example of Yosys template script can be the following:

# Read HDL files
${READ_HDL}

# perform the synthesis
synth -flatten -top ${TOP_MODULE}
# perform LUT mapping
abc -script abc6.scr
# remove unused cells and wires
opt_clean

# write synthesized verilog
write_verilog ${BENCMARK_NAME}
# print stats
stat

@thierryBesson can you please review these requirements and provide your input ?

Create python script which will create new OpenFPGA tasks based on existing ones.

The request for this script comes from OpenFPGA_RS/pull/16.
The script will read input JSON file which will be mainteined in this repository and create new tasks based on the data specified in the input JSON.

Update benchmark paths according latest changes in the RTL_Benchmark repository

There are some updates in the RTL_Benchmark repository which break our Golden suite (All_lut). This task is about to sync our suites with the latest changes in RTL_Benchmark repo.

Update log extractor script.

Currently the following formula is used in the log extractor script to count Vivado LUT: sum up the LUTx in the "Primitives" Table + Carrys + MUXF7 + MUXF8 - Lut as Memory (from the "Slice Logic" table) and percentage of yosys LUT is calculated based on the result of this formula.

The following needs to be done:

1. add 2 additional columns for Vivado:

• Vivado LUT CARRY4=4*LUT - should contain LUT count calculated with the following formula: sum up the LUTx in the "Primitives" Table + 4 * Carrys + MUXF7 + MUXF8 - Lut as Memory (from the "Slice Logic" table)
• Vivado LUT CARRY4=5*LUT - should contain LUT count calculated with the following formula: sum up the LUTx in the "Primitives" Table + 5 * Carrys + MUXF7 + MUXF8 - Lut as Memory (from the "Slice Logic" table)

2. calculate seperate percentages for Yosys based on newly added Vivado LUT CARRY4=4*LUT and Vivado LUT CARRY4=5*LUT columns.

Metrics extraction script

The script should take as input logs directory and produce csv file with below metrics for each benchmark and tool.
We need to extract the following metrics from Yosys and Vivado synth utilization logs:

• Σ LUT
• Σ DFF
• Σ SRL (Shift Register LUT)
• Σ DRAM (Distributed RAM)
• Σ BRAM (Block RAM)
• Σ DSP

In case of Vivado the calculations should be done based on primitives report (7. section in utilization report) as the following formulas :
Σ LUT = Σ LUT* (Ref Name) + Σ MUXF* (Ref Name) + Σ CARRY4 (Ref Name) + Σ INV (Ref Name)
Σ DFF = Σ Flop & Latch (Functional Category)
Σ SRL = Σ SRL* (Ref Name)
Σ DRAM = Σ Distributed Memory (Functional Category) - SRL* (Ref Name) belongs to Distributed Memory (Functional Category) @thierryBesson should we exclude these from Σ DRAM ?
Σ BRAM = Σ Block Memory (Functional Category)
Σ DSP = Σ DSP* (Ref Name)

In case of Yosys the calculations should be done as the following formulas :
Σ LUT = Σ lut
Σ DFF = Σ *dff* + Σ *latch*
Σ SRL = ? needs to be clarified
Σ DRAM = ? needs to be clarified
Σ BRAM = Σ *ram* ? needs to be clarified
Σ DSP = Σ mult* ? needs to be clarified

@thierryBesson could you please provide your input regarding the questions mentioned above ?

Create regression tests suite for the yosys+verific tasks.

Update run_task_generator.py script to generate also regression tests.

Add Makefile for the repository.

The Makefile should have the following targets which might be further enhanced later.

• all - should checkout all submodules, build yosys with verific enabled (should checkout verific-integration branch for yosys_rs repo)
• co_yosys - should checkout yosys submodule
• co_yosys+verific - should checkout yosys submodule verific-integration branch
• co_benchmarks - should checkouut all submodule benchmarks
• co_vhdl - should checkout all VHDL submodule benchmarks
• co_sv - should checkout all SV submodule benchmarks
• co_mixed_language - should checkout all mixed language benchmarks
• co_BENCHMARK_NAME - should checkout BENCHMARK_NAME submodule benchmark
• build_yosys - compile yosys
• build_yosys+verific - compile yosys with Verific enabled
• clean - clean all generated files
• clean_benchmarks - clean all benchmark submodule folders
• help - print help message

OpenFPGA_RS DSP tasks fail when ran with Yosys+Verific.

The following OpenFPGA_RS DSP regression tests are failing VVP verification, which is a result of the DSP module swapped port mapping.

• fpga_verilog/dsp/multi_mode_mult_16x16_verific
• fpga_verilog/dsp/single_mode_mult_8x8_verific
• fpga_verilog/dsp/wide_multi_mode_mult_16x16_verific

In order to reproduce generate OpenFPGA_RS tasks using scripts/task_generator/run_task_generator.py script with the below JSON configuration file and run the generated OpenFPGA_RS tasks.

[aram@khyber yosys_verific_rs]$ cat dsp_tasks.json
[
    {
        "original_task_dir": "fpga_verilog/dsp/multi_mode_mult_16x16",
        "new_task_dir": "fpga_verilog/dsp/multi_mode_mult_16x16_verific",
        "config_sections": {
            "GENERAL": {
                "verific": "true"
            },
            "OpenFPGA_SHELL": {
                "yosys_blackbox_modules": "mult_8,mult_16"
            },
            "SYNTHESIS_PARAM": {
                "bench_yosys_common": "${ROOT_PATH}/scripts/yosys_templates/ys_tmpl_yosys+verific_vpr_dsp_flow.ys",
                "bench_yosys_rewrite_common": "${ROOT_PATH}/scripts/yosys_templates/ys_tmpl_yosys+verific_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys"
            }
        }
    },
    {
        "original_task_dir": "fpga_verilog/dsp/single_mode_mult_8x8",
        "new_task_dir": "fpga_verilog/dsp/single_mode_mult_8x8_verific",
        "config_sections": {
            "GENERAL": {
                "verific": "true"
            },
            "OpenFPGA_SHELL": {
                "yosys_blackbox_modules": "mult_8"
            },
            "SYNTHESIS_PARAM": {
                "bench_yosys_common": "${ROOT_PATH}/scripts/yosys_templates/ys_tmpl_yosys+verific_vpr_dsp_flow.ys",
                "bench_yosys_rewrite_common": "${ROOT_PATH}/scripts/yosys_templates/ys_tmpl_yosys+verific_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys"
            }
        }
    },
    {
        "original_task_dir": "fpga_verilog/dsp/wide_multi_mode_mult_16x16",
        "new_task_dir": "fpga_verilog/dsp/wide_multi_mode_mult_16x16_verific",
        "config_sections": {
            "GENERAL": {
                "verific": "true"
            },
            "OpenFPGA_SHELL": {
                "yosys_blackbox_modules": "mult_8,mult_16"
            },
            "SYNTHESIS_PARAM": {
                "bench_yosys_common": "${ROOT_PATH}/scripts/yosys_templates/ys_tmpl_yosys+verific_vpr_dsp_flow.ys",
                "bench_yosys_rewrite_common": "${ROOT_PATH}/scripts/yosys_templates/ys_tmpl_yosys+verific_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys"
            }
        }
    }
]

Investigate and fix Yosys failures of QL benchmarks which are passing on Vivado.

There are some designs which fail on Yosys but pass on Vivado. We need to investigate and fix these failures. The results are attached
QL.xlsx

Enhancements in OpenFPGA task generator script.

The following enhancements would be useful for a new tests creation:

1. New discard_config_sections property for the Task settings in settings Json file. The property should contain configurations which should not be included in the newly generated task. For example:

[
    {
        "original_task_dir": "basic_tests/k4_series/k4n4_fracff",
        "new_task_dir": "basic_tests/k4_series/k4n4_fracff_verific",
        "config_sections": {
            "GENERAL": {
                "verific": "true"
            },
            "OpenFPGA_SHELL": {
                "yosys_blackbox_modules": "latchre,dffrn,dffre,dff,dffr"
            },
            "SYNTHESIS_PARAM": {
                "bench_yosys_common": "${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys+verific_vpr_dff_flow.ys"
            }
        },
        "discard_config_sections": {
            "SYNTHESIS_PARAM": {
                "bench_yosys_rewrite_common": "${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys+verific_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys"
            }
        }
    }
]

The bench_yosys_rewrite_common configuration should not be present in the newly created task for the provided example. In case if empty dictionary is provided as a value for the configuration section, then all configurations in the section should be discarded.

2. ${ROOT_PATH} variable support in the settings Json file which should be substituted with the yosys_verific_rs repository absolute path during the task generation.

Change all benchmark paths in all suites to the corresponding one in the RTL_Benchmark repository

The RTL_Benchmark repository has been updated to contain all benchmarks (IWLS2005, EPFL, itc99-poli, ql_designs, ...) from different origins. We should use RTL_Benchmark as a storage for all benchmarks and all other repositories should use RTL_Benchmark for the benchmarking. This task is for changing the benchmarks paths in the all existing suites of the yosys_verific_rs repository. In scope of this task we also need to do some cleanup in the suites configurations: we should keep only SUIT_NAME_synth_rs_area.json and SUIT_NAME_vivado.json configurations.

Fix default settings of the task generator script.

The following tasks settings need to be corrected:

• benchmark_sweep/counter_verific
• benchmark_sweep/vtr_benchmarks_verific
• quicklogic_tests/flow_test_verific

Enhance Github 'Weekly Regression tests' action

The following should be done in scope of this task:

• Make logs of the Yosys 0.14+36 (git sha1 15a4e900b, gcc 7.1.0 -fPIC -Os) + Verific vJan22 + Yosys-RS script + ABC-a21 script configuration as an Area optimized golden - area_golden.
• Change run configuration to Yosys 0.14+36 (git sha1 15a4e900b, gcc 7.1.0 -fPIC -Os) + Verific vJan22 + Synth_RS_Area
• Make as a comparison base the area_golden logs.
• Add QoR at the end of the actions which will flag the QoR with the following way:
  • no any degradation and there is an average improvement - GREEN
  • no degradation above 5% and there is an average improvement - BLUE
  • no degradation above 5% and there isn't average improvement - YELLOW
  • there is a degradation above 5% and there is an average improvement - PINK
  • there is a degradation above 5% and there isn't average improvement - RED
• In case if QoR is flagged as RED then the build should be considered as Failed

Add a weekly functional correction testing workflow

Add a weekly functional correction testing workflow which will run on every Friday at 19:30 UTC. This workflow will run the daily regression tests workflow, then it will get the synthesized verilog files from the daily regression tests results and run OneSpin or Formality for all benchmarks.

┆Issue is synchronized with this Jira Bug by Unito

Add verific_rs as a submodule and update Makefile

The latest Verific release has been tested with the Yosys patch. So it is safe to make Verific Nov21 Release with Yosys patch as default Verific library in our setups. Also according to Yosys recomendation we should use the latest Yosys from main branch with the Verific library. This task is about to make verific_rs repository as submodule and update the Makefile accordingly.

Add ISCAS99 VHDL benchmarks

Currently ISCAS99 benchmarks are stored in on khyber server under /tmp/itc99-poli-2 directory. These benchmars need to be included in the yosys_verific_rs repository.

More details in CSV extraction from Vivado report

The following new metrics needs to be added in CSV report for Vivado tool:

• CARRY4
• MUXF7
• MUXF8
• LUT as Logic
• LUT as memory

Compile errors while under Raptor

Checkout the Raptor repo, do a fresh checkout, note it looks for clang (It should use gcc), then errors out at the bottom of the text below:

alain@alain-xps:~/RapidSilicon/Raptor/yosys_verific_rs$ make co_and_build_yosys_verific
cd yosys && make clean
make[1]: Entering directory '/home/alain/RapidSilicon/Raptor/yosys_verific_rs/yosys'
**/bin/sh: 1: clang: not found**
rm -rf share
rm -rf kernel/*.pyh
if test -d manual; then cd manual && sh clean.sh; fi
find ./PRESENTATION_ExSyn/ -name '*.dot' | xargs rm -f
find ./ -name '*.aux' | xargs rm -f
find ./ -name '*.bbl' | xargs rm -f
find ./ -name '*.blg' | xargs rm -f
find ./ -name '*.idx' | xargs rm -f
find ./ -name '*.log' | xargs rm -f
find ./ -name '*.out' | xargs rm -f
find ./ -name '*.pdf' | xargs rm -f
find ./ -name '*.toc' | xargs rm -f
find ./ -name '*.snm' | xargs rm -f
find ./ -name '*.nav' | xargs rm -f
find ./ -name '*.vrb' | xargs rm -f
find ./ -name '*.ok' | xargs rm -f
find ./PRESENTATION_Prog/ -name 'my_cmd.so' | xargs rm -f
find ./PRESENTATION_Prog/ -name 'my_cmd.d' | xargs rm -f
find ./PRESENTATION_ExAdv/ -name '*.dot' | xargs rm -f
find ./PRESENTATION_Intro/ -name 'counter_00.dot' | xargs rm -f
find ./PRESENTATION_Intro/ -name 'counter_01.dot' | xargs rm -f
find ./PRESENTATION_Intro/ -name 'counter_02.dot' | xargs rm -f
find ./PRESENTATION_Intro/ -name 'counter_03.dot' | xargs rm -f
find ./CHAPTER_Prog/ -name 'stubnets.so' | xargs rm -f
find ./CHAPTER_Prog/ -name 'stubnets.d' | xargs rm -f
find ./CHAPTER_Prog/ -name '*.log' | xargs rm -f
find ./PRESENTATION_ExOth/ -name '*.dot' | xargs rm -f
rm -f kernel/version_c9555c9ad.o kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o kernel/cellaigs.o kernel/celledges.o libs/bigint/BigIntegerAlgorithms.o libs/bigint/BigInteger.o libs/bigint/BigIntegerUtils.o libs/bigint/BigUnsigned.o libs/bigint/BigUnsignedInABase.o libs/sha1/sha1.o libs/json11/json11.o libs/subcircuit/subcircuit.o libs/ezsat/ezsat.o libs/ezsat/ezminisat.o libs/minisat/Options.o libs/minisat/SimpSolver.o libs/minisat/Solver.o libs/minisat/System.o frontends/aiger/aigerparse.o frontends/ast/ast.o frontends/ast/simplify.o frontends/ast/genrtlil.o frontends/ast/dpicall.o frontends/blif/blifparse.o frontends/ilang/ilang_parser.tab.o frontends/ilang/ilang_lexer.o frontends/ilang/ilang_frontend.o frontends/json/jsonparse.o frontends/liberty/liberty.o frontends/rpc/rpc_frontend.o frontends/verific/verific.o frontends/verilog/verilog_parser.tab.o frontends/verilog/verilog_lexer.o frontends/verilog/preproc.o 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passes/equiv/equiv_induct.o passes/equiv/equiv_struct.o passes/equiv/equiv_purge.o passes/equiv/equiv_mark.o passes/equiv/equiv_opt.o passes/fsm/fsm.o passes/fsm/fsm_detect.o passes/fsm/fsm_extract.o passes/fsm/fsm_opt.o passes/fsm/fsm_expand.o passes/fsm/fsm_recode.o passes/fsm/fsm_info.o passes/fsm/fsm_export.o passes/fsm/fsm_map.o passes/hierarchy/hierarchy.o passes/hierarchy/uniquify.o passes/hierarchy/submod.o passes/memory/memory.o passes/memory/memory_dff.o passes/memory/memory_share.o passes/memory/memory_collect.o passes/memory/memory_unpack.o passes/memory/memory_bram.o passes/memory/memory_map.o passes/memory/memory_memx.o passes/memory/memory_nordff.o passes/opt/opt.o passes/opt/opt_merge.o passes/opt/opt_mem.o passes/opt/opt_muxtree.o passes/opt/opt_reduce.o passes/opt/opt_rmdff.o passes/opt/opt_share.o passes/opt/opt_clean.o passes/opt/opt_expr.o passes/opt/share.o passes/opt/wreduce.o passes/opt/opt_demorgan.o passes/opt/rmports.o passes/opt/opt_lut.o passes/opt/opt_lut_ins.o passes/opt/pmux2shiftx.o passes/opt/muxpack.o passes/pmgen/test_pmgen.o passes/pmgen/ice40_dsp.o passes/pmgen/ice40_wrapcarry.o passes/pmgen/xilinx_dsp.o passes/pmgen/peepopt.o passes/pmgen/xilinx_srl.o passes/proc/proc.o passes/proc/proc_prune.o passes/proc/proc_clean.o passes/proc/proc_rmdead.o passes/proc/proc_init.o passes/proc/proc_arst.o passes/proc/proc_mux.o passes/proc/proc_dlatch.o passes/proc/proc_dff.o passes/sat/sat.o passes/sat/freduce.o passes/sat/eval.o passes/sat/sim.o passes/sat/miter.o passes/sat/expose.o passes/sat/assertpmux.o passes/sat/clk2fflogic.o passes/sat/async2sync.o passes/sat/supercover.o passes/sat/fmcombine.o passes/sat/mutate.o passes/sat/cutpoint.o passes/sat/fminit.o passes/techmap/techmap.o passes/techmap/simplemap.o passes/techmap/dfflibmap.o passes/techmap/maccmap.o passes/techmap/libparse.o passes/techmap/abc.o passes/techmap/abc9.o passes/techmap/abc9_exe.o passes/techmap/abc9_ops.o passes/techmap/iopadmap.o passes/techmap/clkbufmap.o passes/techmap/hilomap.o passes/techmap/extract.o passes/techmap/extract_fa.o passes/techmap/extract_counter.o passes/techmap/extract_reduce.o passes/techmap/alumacc.o passes/techmap/dff2dffe.o passes/techmap/dffinit.o passes/techmap/pmuxtree.o passes/techmap/muxcover.o passes/techmap/aigmap.o passes/techmap/tribuf.o passes/techmap/lut2mux.o passes/techmap/nlutmap.o passes/techmap/dffsr2dff.o passes/techmap/shregmap.o passes/techmap/deminout.o passes/techmap/insbuf.o passes/techmap/attrmvcp.o passes/techmap/attrmap.o passes/techmap/zinit.o passes/techmap/dff2dffs.o passes/techmap/flowmap.o passes/techmap/extractinv.o passes/tests/test_autotb.o passes/tests/test_cell.o passes/tests/test_abcloop.o backends/aiger/aiger.o backends/aiger/xaiger.o backends/blif/blif.o backends/btor/btor.o backends/edif/edif.o backends/firrtl/firrtl.o backends/ilang/ilang_backend.o backends/intersynth/intersynth.o backends/json/json.o backends/simplec/simplec.o backends/smt2/smt2.o backends/smv/smv.o backends/spice/spice.o backends/table/table.o backends/verilog/verilog_backend.o techlibs/achronix/synth_achronix.o techlibs/anlogic/synth_anlogic.o techlibs/anlogic/anlogic_eqn.o techlibs/anlogic/anlogic_fixcarry.o techlibs/common/synth.o techlibs/common/prep.o techlibs/coolrunner2/synth_coolrunner2.o techlibs/coolrunner2/coolrunner2_sop.o techlibs/coolrunner2/coolrunner2_fixup.o techlibs/easic/synth_easic.o techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_ffinit.o techlibs/ecp5/ecp5_gsr.o techlibs/efinix/synth_efinix.o techlibs/efinix/efinix_gbuf.o techlibs/efinix/efinix_fixcarry.o techlibs/gowin/synth_gowin.o techlibs/gowin/determine_init.o techlibs/greenpak4/synth_greenpak4.o techlibs/greenpak4/greenpak4_dffinv.o techlibs/ice40/synth_ice40.o techlibs/ice40/ice40_braminit.o techlibs/ice40/ice40_ffssr.o techlibs/ice40/ice40_ffinit.o techlibs/ice40/ice40_opt.o techlibs/intel/synth_intel.o techlibs/sf2/synth_sf2.o techlibs/sf2/sf2_iobs.o techlibs/xilinx/synth_xilinx.o techlibs/xilinx/xilinx_dffopt.o frontends/ilang/ilang_parser.tab.cc frontends/ilang/ilang_parser.tab.hh frontends/ilang/ilang_parser.output frontends/ilang/ilang_lexer.cc frontends/verilog/verilog_parser.tab.cc frontends/verilog/verilog_parser.tab.hh frontends/verilog/verilog_parser.output frontends/verilog/verilog_lexer.cc passes/techmap/techmap.inc techlibs/common/simlib_help.inc techlibs/common/simcells_help.inc techlibs/ice40/brams_init1.vh techlibs/ice40/brams_init2.vh techlibs/ice40/brams_init3.vh techlibs/xilinx/brams_init_36.vh techlibs/xilinx/brams_init_32.vh techlibs/xilinx/brams_init_18.vh techlibs/xilinx/brams_init_16.vh techlibs/xilinx/brams_init_9.vh techlibs/xilinx/brams_init_8.vh yosys yosys-config yosys-abc yosys-filterlib yosys-smtbmc share/include/kernel/yosys.h share/include/kernel/hashlib.h share/include/kernel/log.h share/include/kernel/rtlil.h share/include/kernel/register.h share/include/kernel/celltypes.h share/include/kernel/celledges.h share/include/kernel/consteval.h share/include/kernel/sigtools.h share/include/kernel/modtools.h share/include/kernel/macc.h share/include/kernel/utils.h share/include/kernel/satgen.h share/include/libs/ezsat/ezsat.h share/include/libs/ezsat/ezminisat.h share/include/libs/sha1/sha1.h share/include/libs/json11/json11.hpp share/include/passes/fsm/fsmdata.h share/include/frontends/ast/ast.h share/include/backends/ilang/ilang_backend.h share/python3/smtio.py share/achronix/speedster22i/cells_sim.v share/achronix/speedster22i/cells_map.v share/anlogic/cells_map.v share/anlogic/arith_map.v share/anlogic/cells_sim.v share/anlogic/eagle_bb.v share/anlogic/lutrams.txt share/anlogic/lutrams_map.v share/anlogic/lutram_init_16x4.vh share/simlib.v share/simcells.v share/techmap.v share/pmux2mux.v share/adff2dff.v share/dff2ff.v share/gate2lut.v share/cmp2lut.v share/cells.lib share/mul2dsp.v share/abc9_model.v share/coolrunner2/cells_latch.v share/coolrunner2/cells_sim.v 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share/gowin/bram_init_16.vh share/greenpak4/cells_blackbox.v share/greenpak4/cells_latch.v share/greenpak4/cells_map.v share/greenpak4/cells_sim.v share/greenpak4/cells_sim_ams.v share/greenpak4/cells_sim_digital.v share/greenpak4/cells_sim_wip.v share/greenpak4/gp_dff.lib share/ice40/arith_map.v share/ice40/cells_map.v share/ice40/cells_sim.v share/ice40/latches_map.v share/ice40/brams.txt share/ice40/brams_map.v share/ice40/dsp_map.v share/ice40/abc9_model.v share/ice40/brams_init1.vh share/ice40/brams_init2.vh share/ice40/brams_init3.vh share/intel/common/m9k_bb.v share/intel/common/altpll_bb.v share/intel/common/brams_m9k.txt share/intel/common/brams_map_m9k.v share/intel/max10/cells_sim.v share/intel/arria10gx/cells_sim.v share/intel/cyclonev/cells_sim.v share/intel/cyclone10lp/cells_sim.v share/intel/cycloneiv/cells_sim.v share/intel/cycloneive/cells_sim.v share/intel/max10/cells_map.v share/intel/arria10gx/cells_map.v share/intel/cyclonev/cells_map.v share/intel/cyclone10lp/cells_map.v share/intel/cycloneiv/cells_map.v share/intel/cycloneive/cells_map.v share/sf2/arith_map.v share/sf2/cells_map.v share/sf2/cells_sim.v share/xilinx/cells_map.v share/xilinx/cells_sim.v share/xilinx/cells_xtra.v share/xilinx/xc2v_brams.txt share/xilinx/xc2v_brams_map.v share/xilinx/xc3sa_brams.txt share/xilinx/xc3sda_brams.txt share/xilinx/xc6s_brams.txt share/xilinx/xc6s_brams_map.v share/xilinx/xc7_xcu_brams.txt share/xilinx/xc7_brams_map.v share/xilinx/xcu_brams_map.v share/xilinx/xcup_urams.txt share/xilinx/xcup_urams_map.v share/xilinx/lut4_lutrams.txt share/xilinx/lut6_lutrams.txt share/xilinx/lutrams_map.v share/xilinx/arith_map.v share/xilinx/xc6s_ff_map.v share/xilinx/xc7_ff_map.v share/xilinx/lut_map.v share/xilinx/mux_map.v share/xilinx/xc3s_mult_map.v share/xilinx/xc3sda_dsp_map.v share/xilinx/xc6s_dsp_map.v share/xilinx/xc4v_dsp_map.v share/xilinx/xc5v_dsp_map.v share/xilinx/xc7_dsp_map.v share/xilinx/xcu_dsp_map.v share/xilinx/abc9_map.v share/xilinx/abc9_unmap.v share/xilinx/abc9_model.v share/xilinx/brams_init_36.vh share/xilinx/brams_init_32.vh share/xilinx/brams_init_18.vh share/xilinx/brams_init_16.vh share/xilinx/brams_init_9.vh share/xilinx/brams_init_8.vh passes/pmgen/test_pmgen_pm.h passes/pmgen/ice40_dsp_pm.h passes/pmgen/ice40_wrapcarry_pm.h passes/pmgen/xilinx_dsp_pm.h passes/pmgen/xilinx_dsp48a_pm.h passes/pmgen/xilinx_dsp_CREG_pm.h passes/pmgen/xilinx_dsp_cascade_pm.h passes/pmgen/peepopt_pm.h passes/pmgen/xilinx_srl_pm.h passes/techmap/filterlib.o techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk techlibs/gowin/brams_init.mk techlibs/ice40/brams_init.mk techlibs/xilinx/brams_init.mk  .cc
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make[1]: Leaving directory '/home/alain/RapidSilicon/Raptor/yosys_verific_rs/yosys'
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**make[2]: Entering directory '/home/alain/RapidSilicon/Raptor/yosys_verific_rs/yosys-plugins/fasm-plugin'
../Makefile_plugin.common:47: *** "Didn't find 'yosys-config' under '/'".  Stop.**
make[2]: Leaving directory '/home/alain/RapidSilicon/Raptor/yosys_verific_rs/yosys-plugins/fasm-plugin'
make[1]: *** [Makefile:37: clean_fasm] Error 2
make[1]: Leaving directory '/home/alain/RapidSilicon/Raptor/yosys_verific_rs/yosys-plugins'
make: *** [Makefile:196: clean_yosys] Error 2
alain@alain-xps:~/RapidSilicon/Raptor/yosys_verific_rs$ 

Compare QoR results of Vivado Synth and Yosys with/without Verific for all RTL_Benchmark benchmarks.

QoR issue in Yosys+verilog verific synthesis compare to Yosys verilog built-in

I made a few experiments on this repo. by comparing Vivado versus Yosys+Verific (YV) on design "b19.vhd" which is a well known ISCAS99 benchmark. Vivado synthesis return a bit more than 17K Lut6 and Yosys+verific more than 34K Lut6.

I investigated a bit to understand this 2X huge increase and analyze a smaller test case which is "b03.vhd".
"b03.vhd" get 21 LUT6 with Vivado and 28 LUT6 with YV. It is basically a simple FSM.

Now I translated with a small utility (vhd2vl) the "b03.vhd" into its verilog counterpart i.e. "b03.v".
If I call vivado on it I still get 21 Lut6 (which is expected) and I still get 28 Lut6 with Yosys-Verific on verilog which is again consistent.

Now if I use the Yosys verilog built-in parser instead of Verific, I get 21 Lut6 the same as Vivado !

So one explanation of this QoR loss is due to the way we process things in Verific and we proved it on the verilog input side.

We need to address this and understand what is going on. This may be not sufficient to recover the QoR loss on "b19" but it should help.

Now we will receive the new patch from Yosys to get a better bridge between Verific and Yosys (should fix the RTL failures) so we will see if this fixes also the QoR issue reported just right here.

Aram, I keep you posted when we get access to this new patch. I should be able to access it pretty soon.

Add QuickLogic plugin for yosys as a submodule.

This is required to enable QuickLogic sythesis pass.

Perform benchmarking of new 110 QL and IWLS2005 designs.

The new designs/benchmarks are available in yosys_verifc_rs repository:

• benchmarks/verilog
• benchmarks/vhdl/IWLS2005

Create benchmarks suite for the VHDL benchmarks and collect QoR results.

Create JSON suite file for the VHDL benchmarks and run the suite for the following 3 tool configurations:

• Vivado
• yosys-verific-lut6
• yosys-verific-abc-v1.1

The list of verified synthesizeble benchmarks can be found here.

Change weekly regression tests to daily.

Change the existing weekly regression tests setup (workflow) to daily - run every day from Monday till Thursday at 19:30 UTC.

Integrate DE (design explorer) prototype

The prototype implementation is currently available at /home/users/SHARE/thierry/DE/de.tar in the khyber server, which contains :

• ABC files modified for the support of "&de" command : abc.c, gia.h and giaMan.c
• DE core file : de.c
• Quick makefile : ./comp
• ABC scripts called by Yosys in the Yosys script : ade.scr (area), dde.scr (delay) and mde.scr (mixed)
• rs.ys : a typical RS yosys script calling either 'ade.scr' or 'dde.scr' or 'mde.scr'.

To make the engine running the following env variables should be exported:

• ABC : the ABC executable path
• DE : the DE executable path.

Use /home/users/SHARE/thierry/DE/de.c which has a better informative formatting for output results.

A first document explaining how DE works and how to use it and integrate it it attached.

de_doc.odt

This task is about to pick up the files above and create a sub-module of name "design_explorer" under 'logic_synthesis-rs" repo to add the "de.c" file into it and put the customized abc.c, gia.h and giaMan.c files under the customized ABC directory "abc-rs".

No info if the benchmark path is wrong.

Currently if user doesn't checkout RTL_Benchmark repository in yosys_verific_rs (make co_rtl_benchmark) and runs All_lut suite then the results log file shows only 2 benchmarks are run, but there are 60 benchmarks in the suite. This behavior is incorrect - the synthesis.py script should report the the 58 benchmarks were not run (failed) due to missing sources.

[bella@khyber yosys_verific_rs]$ python3 scripts/synth/synthesis.py --config_files suites/All/All_lut_synth_rs_area.json 
    INFO - Starting synthesis for configs:
    INFO - 	suites/All/All_lut_synth_rs_area.json
    INFO - Output directory - /home/users/bella/yosys_verific_rs/result_07-03-2022T13-21-44
    INFO - Running synthesis for All_lut_synth_rs_area.json config
    INFO - Starting synthesis run of systemcdes for configuration All_lut_synth_rs_area.json
    INFO - Starting synthesis run of iir for configuration All_lut_synth_rs_area.json
    INFO - Successfully completed synthesis run of systemcdes for configuration All_lut_synth_rs_area.json in 21.852405786514282 seconds.
    INFO - Successfully completed synthesis run of iir for configuration All_lut_synth_rs_area.json in 31.225849151611328 seconds.
    INFO - Finished synthesis for All_lut_synth_rs_area.json config in 31.38594150543213 seconds
    INFO - Synthesis run completed in 31.387972593307495 seconds.

Update the README file.

Update the readme file with short descriptions of the repository and it's structure.

Integrate yosys-rs-plugin with yosys_verific_rs repository.

The following should be done in scope of this task:

• make yosys-rs-plugin repository as a submodule of the yosys_verific_rs repostitory
• update yosys_verific_rs makefile to build also yosys-rs-plugin
• add new yosys_template_synth_rs.ys temlate script which will use synth_rs command
• create new JSON configuration files for all existing suites to use the new yosys_template_synth_rs.ys temlate script

Research to find Verilog version of the ISCAS99 benchmarks.

The Verilog version will be used to make sure that synthesis leads to same QoR data on both versions (VHDL and Verilog).

Upgrade Verific version to Feb22

The Verific vFeb22 release is already available, so we need to upgrade our Verific version as well. The following needs to be done:

• create new vFeb22-yosys branch in the verific_rs repo based on vFeb22 branch and apply yosys patch in the newly created branch - for the Yosys patch we need to check with @thierryBesson
• update Makefile of yosys_verific_rs to use the vFeb22-yosys branch of the verific_rs repo
• Run All_lut suite with Verific vFeb22 and vJan22 releases, compare QoR - creaet PR with the QoR data.