Comments (2)
您好,error_delayed
这个信号没有考虑使能信号,您还需要从波形里面关注一下读使能是否有效以及是否存在 bank 冲突:
(0 until LoadPipelineWidth).map(i => {
// ... ...
(0 until VLEN/DCacheSRAMRowBits).map( j =>{
io.read_resp_delayed(i)(j) := bank_result_delayed(rr_div_addr)(rr_bank_addr(j))
// error detection
io.read_error_delayed(i)(j) := rr_read_fire && read_bank_error_delayed(rr_div_addr)(rr_bank_addr(j)) && !RegNext(io.bank_conflict_slow(i))
})
})
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多谢。commit 62dfd6c3b0f051d061f4e8c2c855ef69ecba0d94上没有这处的改动,我再试试最新的代码。
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