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or1k_marocchino's Issues

Setup FPU test environment for or1k_marocchino

Creating this item as work to discuss how to setup the FPU test environment for the marocchino FPU.

  • Main Linux + GLIBC Math tests
  • Bare metal - TestFloat

Other questions:
By the way. Are your planning just to add marocchino for arty SoC or also to add atlys SoC to litex project?

FPU exceptions set incorrect EPCR

According to the spec 6.3 Exception Processing. For FPU exceptions the EPCR should be set to Address of next not executed instruction.

This is the same as Tick Timer, External Interrupt and Syscall.

It seems currently FPU exceptions are being set to Address of instruction that caused exception. This is causing tests to fail.

Test: https://github.com/openrisc/binutils-gdb/blob/orfpx64a32/sim/testsuite/sim/or1k/fpu64a32.S

fusesoc run --target marocchino_tb --tool icarus mor1kx-generic --elf-load ./fpu64a32.S.x --trace_enable --trace_to_screen

S 00000d38: 24000000 l.rfe                                          flag: 1
// Instruction that caused the failure.
S 00002370: c84c0013 lf.div.d  r2,r12,r0                            flag: 1
S 00000d00: 9c21ff80 l.addi  r1,r1,0xff80    r1         = 000033bc  flag: 1
S 00000d04: 9c21fffc l.addi  r1,r1,0xfffc    r1         = 000033b8  flag: 1
S 00000d08: d4011000 l.sw    0x0000(r1),r2   [000033b8] = 00000001  flag: 1
S 00000d0c: 9c21fffc l.addi  r1,r1,0xfffc    r1         = 000033b4  flag: 1
S 00000d10: d4011800 l.sw    0x0000(r1),r3   [000033b4] = 00002054  flag: 1
// EPCR was loaded with 0x2370
S 00000d14: b4400020 l.mfspr r2,r0,0x0020    r2         = 00002370  flag: 1
S 00000d18: 18601500 l.movhi r3,0x1500       r3         = 15000000  flag: 1
S 00000d1c: a8630000 l.ori   r3,r3,0x0000    r3         = 15000000  flag: 1
S 00000d20: d7e21ffc l.sw    0xfffc(r2),r3   [0000236c] = 15000000  flag: 1
S 00000d24: 84610000 l.lwz   r3,0x0000(r1)   r3         = 00002054  flag: 1
S 00000d28: 9c210004 l.addi  r1,r1,0x0004    r1         = 000033b8  flag: 1
S 00000d2c: 84410000 l.lwz   r2,0x0000(r1)   r2         = 00000001  flag: 1
S 00000d30: 9c210004 l.addi  r1,r1,0x0004    r1         = 000033bc  flag: 1
S 00000d34: 9c210080 l.addi  r1,r1,0x0080    r1         = 0000343c  flag: 1
S 00000d38: 24000000 l.rfe                                          flag: 1
S 00002370: c84c0013 lf.div.d  r2,r12,r0                            flag: 1
S 00000d00: 9c21ff80 l.addi  r1,r1,0xff80    r1         = 000033bc  flag: 1
S 00000d04: 9c21fffc l.addi  r1,r1,0xfffc    r1         = 000033b8  flag: 1
S 00000d08: d4011000 l.sw    0x0000(r1),r2   [000033b8] = 00000001  flag: 1

Booting Linux Failing

I have setup or1k_marocchino to run on the digilent arty using Litex. See: enjoy-digital/litex#1161

However, linux is not booting. So far I have traced this to go wrong during:
init/main.c
mm_init()
- kmem_cache_init() - somewhere in here it gets stuck looking on dlb misses

Output of: fusesoc run --target marocchino_tb mor1kx-generic --option_rf_num_shadow_gpr 1 --elf_load /home/shorne/work/linux/vmlinux --trace_enable 

--
_raw_spin_lock_irqsave()
 itlb miss

S c05e2b20: e0729004 l.or    r3,r18,r18      r3         = c0800020  flag: 0
S c05e2b20: e0729004 l.or    r3,r18,r18      r3         = c0800020  flag: 0
S 00000a00: 000005e0 l.j     0x00005e0                              flag: 0
S 00000a04: 15000000 l.nop   0x0000                                 flag: 0
S 00002180: c0001422 l.mtspr r0,r2,0x0422    SPR[0422]  = c06b7ee0  flag: 0
S 00002184: c0001c23 l.mtspr r0,r3,0x0423    SPR[0423]  = c0800020  flag: 0
S 00002188: c0002424 l.mtspr r0,r4,0x0424    SPR[0424]  = 00000900  flag: 0
--
kmem_cache_alloc()

S c0119c54: 8702fffc l.lwz   r24,0xfffc(r2)  r24        = c0753984  flag: 1
S c0119c54: 8702fffc l.lwz   r24,0xfffc(r2)  r24        = c0753984  flag: 1
S 00000a00: 000005e0 l.j     0x00005e0                              flag: 1
S 00000a04: 15000000 l.nop   0x0000                                 flag: 1
S 00002180: c0001422 l.mtspr r0,r2,0x0422    SPR[0422]  = c06b7f2c  flag: 1
S 00002184: c0001c23 l.mtspr r0,r3,0x0423    SPR[0423]  = c0802000  flag: 1
S 00002188: c0002424 l.mtspr r0,r4,0x0424    SPR[0424]  = 00000100  flag: 1
--
strlen (c0683a23)

S c05c8644: e1631804 l.or    r11,r3,r3       r11        = c0683a23  flag: 1
S c05c8648: 922b0000 l.lbs   r17,0x0000(r11) r17        = 00000008  flag: 1
S 00000900: 000005c0 l.j     0x00005c0                              flag: 1
S 00000904: 15000000 l.nop   0x0000                                 flag: 1
S 00002000: c0774610 l.mtspr r23,r8,0x1e10   SPR[3f30]  = 00000008  flag: 1
S 00002004: 00002000 l.j     0x0002000                              flag: 1
S 00002008: 00000005 l.j     0x0000005                              flag: 1
--
STRLEN
S 00002254: 24000000 l.rfe                                          flag: 0
S c05c8648: 922b0000 l.lbs   r17,0x0000(r11) r17        = 00000008  flag: 1
S 00000900: 000005c0 l.j     0x00005c0                              flag: 1
S 00000904: 15000000 l.nop   0x0000                                 flag: 1
S 00002000: c0774610 l.mtspr r23,r8,0x1e10   SPR[3f30]  = 00000008  flag: 1
S 00002004: 00002000 l.j     0x0002000                              flag: 1
S 00002008: 00000005 l.j     0x0000005                              flag: 1

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