onkolahmet / cachelab

simulating hit/miss behavior of cache memory

Cachelab

It's a basic cache simulator which takes an image of memory and a memory trace as input, simulates the hit/miss behavior of a cache memory on this trace, and outputs the total number of hits, misses, and evictions for each cache type along with the content of each cache at the end.

Reference Trace Files

The traces subdirectory of the handout directory contains a collection of reference trace files that we will use to evaluate the correctness of the cache simulator you write. The memory trace files have the following form:

M 000ebe20, 3, 58a35a
L 000eaa30, 6
S 0003b020, 7, abb2cdc69bb454
I 00002010, 6

Each line denotes one or two memory accesses. The format of each line for I and L:
operation address, size.

The format of each line for M and S:
operation address, size, data.

The operation field denotes the type of memory access:

• “I” denotes an instruction load,
• “L” a data load,
  
• “S” a data store, and
  
• “M” a data modify (i.e., a data load followed by a data store).
  

The address field specifies a 32-bit hexadecimal memory address.

The size field specifies the number of bytes accessed by the operation.

The data field specifies the data bytes stored in the given address.

Example Run

Hit/Miss Behavior of a Cache Memory