Select stage to run in core file about fusesoc

[olofk]

The behaviour of trying to program the FPGA is indeed a bit problematic and inconsistent between different backends and has been bugging me for a long time (see e.g. here #319 ) . I do have a slightly different idea of how to solve this though. My proposal is to never program by default, and instead add a flow option, say --pgm to the relevant Edalize flows to opt-in programming. flow options can be set in the target already so that we can program by default if we want to.

While we're on the topic, I would also like to see some configurability when it comes to the device programming tools so that we can select which programming tool to use and set options

Ideally I would also like to see an external library that handles the FPGA programming instead of having that in Edalize, so that every build tool (Edalize, SiliconCompiler, Litex etc) could share that code.

[GCHQDeveloper211]

If this were to happen, would that mean that the "build" stage and the "run" stage of a PNR build essentially become the same thing?