This is a dynamic programmable clock divider, providing a symmetric clock output with a glitch-free frequency division switching.
I. Brynjolfson and Z. Zilic, "Dynamic clock management for low power applications in FPGAs," Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044), Orlando, FL, USA, 2000, pp. 139-142, doi: 10.1109/CICC.2000.852635.