Comments (8)
This might be an issue I've seen before. If you look at the first screenshot on the readme you'll see there's a redundant line to count_out. It's due to the way that ELK doesn't really handle hyper edges.
I probably made it even worse when I added "lateral port" handling a while back.
I'll need to add a step to search for these redundant wires and delete it down to the minimum number required to connect all of the ports.
from netlistsvg.
Are you setting postCompaction now? #40 (comment)
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I need to write up a document of all of the types of bad layouts.
I think ELK is tracking this issue here: eclipse/elk#374
I just added postCompaction the other day but it probably won't help with this particular issue.
from netlistsvg.
Here's the latest output (pulled a few hours ago) for my schematic: https://google.github.io/pcbdl/examples/servo_micro.svg
You can still see the same problem around U7 and U3.
postCompaction did make a lot of things shorter, I like that.
from netlistsvg.
It looks like youd benefit from wide nodes on multiple layers. We should try turning that on the analog skin as well. https://www.eclipse.org/elk/reference/options/org-eclipse-elk-layered-layering-widenodesonmultiplelayers.html
from netlistsvg.
I feel like I'm doing something wrong when trying to enable this.
It has no effect. But to be fair, even if I had typos it wouldn't complain about it
diff --git a/lib/analog.svg b/lib/analog.svg
index 0ef2d2e..6956616 100644
--- a/lib/analog.svg
+++ b/lib/analog.svg
@@ -9,6 +9,7 @@
org.eclipse.elk.layered.spacing.nodeNodeBetweenLayers="5"
layered.compaction.postCompaction.strategy="4"
elk.spacing.nodeNode= "35"
+ org.eclipse.elk.layered.layering.wideNodesOnMultipleLayers="AGGRESSIVE"
org.eclipse.elk.direction="DOWN"/>
<s:low_priority_alias val="$dff" />
</s:properties>
from netlistsvg.
odd, I would've thought that would do something more interesting from the description.
from netlistsvg.
I can only assume I didn't enable it properly.
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Related Issues (20)
- Wires laid out atop one another HOT 2
- Shorted outputs don't work in the presence of split nodes HOT 1
- Can not draw svg with a "hardcoded FPGA block" HOT 2
- Exported svg is using "physical wiring connections" instead of "signal name association" (netlists) HOT 4
- Request: Padding
- TypeError: Cannot read property 'startsWith' of undefined at built/Skin.js:11 HOT 5
- patch for correct OR and NOR gates shapes in default.svg HOT 1
- Node v12 doesn't resolve dependancies HOT 1
- Text is getting cropped
- New version? HOT 1
- Module name used instead of Instance name for generic cells
- Render attribute as label on wires
- How to decode this error message? HOT 1
- $_ANDNOT gate is rendered as $_NAND HOT 4
- The generated schematics are corrupted around the (AND) cell. HOT 2
- wires
- output pin doesn't connect to anything HOT 1
- Add css media queries to support dark themes HOT 1
- Forcing bits on a bus to be ordered numerically HOT 1
- could you please commit and maintain a package lock file? HOT 1
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