nic30 / hwtlib Goto Github PK

https://github.com/eltvor/zlogan

The problem is that the DMA logic for bus interfaces is fragmented over multiple components which do something similar, but in a different way. There is a problem is also support for out-of-order which complicates the things.
Because of this we need a single implementation of read and write component (separately) which will be easily configurable.

Expected functionality:

(from Axi_r/wDatapump)

• If data is larger than max frame on target bus split it on multiple frames on bus but act as a single frame on driver side

(from StructReader/Writer)

• describe the data using data type + transaction template (not just max frame len) because we need this for alignment analysis and frame split analysis
• this means we should be also able to describe dense data structures (padding)

(from ArrayItemGetter, AddrDataHs_to_Axi)

• if data is smaller than bus word, roundup the address and construct the part selection logic for data word

(from StructReader/Writer and ArrayItemGetter)

• ability to specify also the alignment of the start of the data
• ability to automatically generate padding to best fit for data smaller and larger than the bus word

(from RamAsHs)

• support for latency synchronized buses like BRAM port or some versions of Avalon-MM

It is also expected that the implementation will be just some kind of manager which will generate required logic (that means that this will not be an independent component.) The reason for this is to allow conditional modification of local memory resources in current component without need for generating a complex IO of bus connector.

Hi,

a lot of the more elaborate examples do not work. This seems mostly because of API changes that were made in the past.

A baseline pip install hwtlib hwt as well as the latest git master clone will give the same issues.

For the StructReader, I see this error:

   from hwtLib.amba.datapump.intf import AxiRDatapumpIntf
ModuleNotFoundError: No module named 'hwtLib.amba.datapump'

For other examples there are other errors. But all i have traced back is linked to changed APIs (imports or function names).

This makes is really hard to understand some advanced concepts because there is not much documentation except the examples. I strongly recommed to add the examples to a regression suite so it does not break.

regards
Philip

https://github.com/pulp-platform/common_cells/blob/master/src/cb_filter.sv

https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/manual/mnl_avalon_spec.pdf

There are tests just not for the top.

http://www.embecosm.com/appnotes/ean5/embecosm-systemc-jtag-cycle-acc-ean5-issue-1.html

https://github.com/www-asics-ws/usb1_device
https://github.com/lambdaconcept/usbsniffer/releases
https://github.com/ultraembedded/riscv_sbc
https://github.com/mrrb/tfg
https://sites.google.com/site/vysakhppillai/technical-articles/universal-serial-bus
https://github.com/im-tomu/valentyusb
https://github.com/hdl4fpga/hdl4fpga/blob/master/ULX3S/scopeio/usbserial_rxd.vhd
https://github.com/tinyfpga/TinyFPGA-Bootloader/tree/master/common
https://github.com/timvideos/HDMI2USB-numato-opsis-sample-code/tree/master/comms/ulpi
https://github.com/enjoy-digital/usb3_pipe
https://github.com/greatscottgadgets/luna

https://github.com/enjoy-digital/litex/tree/ea8be6adcd4b76fdc7c0548a8bf9601ac8b96431/litex/soc/cores/clock
amaranth-lang/amaranth#425

After Verilator integration, pci-e components will be moved to this public repo

Union type which will allow much easier implementation use of parsers and frame builders

Hi, I get this error when trying to execute the code in SimpleUnit example:

Traceback (most recent call last):
  File "hwt_components/test.py", line 45, in <module>
    from hwt.synthesizer.utils import to_rtl_str
  File "/home/welberthime/.local/lib/python3.6/site-packages/hwt/synthesizer/utils.py", line 8, in <module>
    from hwt.serializer.vhdl import Vhdl2008Serializer
  File "/home/welberthime/.local/lib/python3.6/site-packages/hwt/serializer/vhdl/__init__.py", line 5, in <module>

    from hwt.serializer.vhdl.serializer import ToHdlAstVhdl2008
  File "/home/welberthime/.local/lib/python3.6/site-packages/hwt/serializer/vhdl/serializer.py", line 11, in <module>
    from hwt.serializer.vhdl.ops import ToHdlAstVhdl2008_ops
  File "/home/welberthime/.local/lib/python3.6/site-packages/hwt/serializer/vhdl/ops.py", line 14, in <module>
    from hwt.serializer.hwt.ops import ToHdlAstHwt_ops
  File "/home/welberthime/.local/lib/python3.6/site-packages/hwt/serializer/hwt/__init__.py", line 5, in <module>
    from hwt.serializer.hwt.serializer import ToHdlAstHwt
  File "/home/welberthime/.local/lib/python3.6/site-packages/hwt/serializer/hwt/serializer.py", line 11, in <module>
    from hwt.serializer.hwt.ops import ToHdlAstHwt_ops
  File "/home/welberthime/.local/lib/python3.6/site-packages/hwt/serializer/hwt/ops.py", line 7, in <module>
    from hwt.serializer.generic.ops import HWT_TO_HDLCONVEROTR_OPS
  File "/home/welberthime/.local/lib/python3.6/site-packages/hwt/serializer/generic/ops.py", line 23, in <module>
    AllOps.ADD,
  File "/home/welberthime/.local/lib/python3.6/site-packages/hwt/serializer/generic/ops.py", line 6, in <dictcomp>
    **{op: getattr(HdlOpType, op.id) for op in [
  File "/usr/lib/python3.6/enum.py", line 326, in __getattr__
    raise AttributeError(name) from None
AttributeError: NEQ

• AxiBuff
• AxiFifoAsync
• AxiStaticRemap
• AxiSFifoAsync

https://github.com/Nic30/hwt/blob/master/hwt/serializer/mode.py

Each value which is agent sending or receiving should have working callback to simplify verification and to add better support for asynchronous programming for tests.

Router mux is generated even if the master can not be connected with this slave.

HStream should be array of arbitrary size with.
HStream will come in handy in frame parsers/forges etc., when we need to describe fields in structure with arbitrary size.