nic30 / hdlconvertorast Goto Github PK

https://github.com/Nic30/hdlConvertorAst/blob/master/hdlConvertorAst/hdlAst/_statements.py#L100

elifs property can be used instead, it would simplify the code analysis as code for elifs has to be there and if then block behaves just as another elif block

job(stm.cond, stm.if_true)
for cond, stms in stm.elifs:
    job(cond, stms)


# is equivalent to

elifs = [(stm.cond, stm.if_true), *stm.elifs]
for cond, stms in elifs:
    job(cond, stms)

# that means we do not need explicit cond, if_true property and we can store it in elifs so the user code does not need 
# another code branch

NOTE: This was modified to include multiple issues of the same or relevant types

Hi,

Trying to use hdlConvertor to read in some VHDL files, I get the following errors in some of my files, for each error I will post the error message with the piece of code causing it:

ERROR1

FILENAME.vhd:88:2: PackageParser.visitConstant_declaration Conversion to Python object not implemented
    ...constantl:NATURAL:=x'length;...

The line in the package causing the error is this:

function REPEAT (x: STD_LOGIC_VECTOR; n: NATURAL) return STD_LOGIC_VECTOR is
        constant l : NATURAL := x'length;	-- That's the cause
        -- Some other things
begin
        -- Some Code
end function REPEAT;

ERROR2

FILENAME.vhd:38:22: StatementParser.visitLoop_statement - label after Conversion to Python object not implemented
    ...forkinjtoi-1loopbranch:=branchandPropagates_in(k);endloopProp;...

The code responsible for it is (inside a process):

Gen: for j in 0 to i-1 loop
	branch := Generates_in(j);
	Prop: for k in j to i-1 loop
		branch := branch and Propagates_in(k);
	end loop Prop;
	partial := partial or branch;
end loop Gen;

ERROR3

FILENAME.vhd:41:4: EntityParser.visitEntity_declarative_item Conversion to Python object not implemented
    ...constantSTAGE_ELEMENTS:INTEGER:=integer(ceil(real(SIZE)/real(STAGES)));...

The code is (inside an entity):

constant STAGE_ELEMENTS         : INTEGER       := integer(ceil(real(SIZE)/real(STAGES)));

ERROR4

ArchParser.visitConcurrent_assertion_statement Conversion to Python object not implemented

Any assertion would generate this.

NOTES

• I'm using VHDL2008
• I read the files simply as in conv.parse(files, Language.VHDL_2008, [])
• Based on the error messages I assume those are implemented in C++ but not converted to python, so if I use hdlConvertor in C++ instead of python I wouldn't be getting the same errors?

Thanks.

Hi there,
I am trying to call visit_HdlContext in class ToJson to generate json tree. However, I got an error:

• File "/usr/local/lib/python3.8/dist-packages/hdlConvertorAst/to/json.py", line 332, in visit_iHdlExpr
  raise NotImplementedError: Unexpected object of type <class 'hdlConvertor.hdlAst._structural .HdlModuleDec'>

I used the code from notebook in
https://github.com/Nic30/hdlConvertor/blob/master/notebooks/01_parse_and_dump.ipynb
Any solution for this?
Thanks

If I have a port declaration with multiple packed and unpacked dimensions:
input logic [P_PACKED0:0][P_PACKED1:0][P_PACKED2:0] multi_dim_input [0:P_UNPACKED0][0:P_UNPACKED1],
only the first packed dimension is recognised as the port's packed dimension, and the remaining ones are processed as though they are unpacked dimensions.
In my code, where x is the port:

with open(".temp", "w") as f:
  tv = ToVerilog2005(f)
  f.write(str(x))
  tv.visit_port_declr(x)

the output is:
input logic[P_PACKED0:0] multi_dim_input [P_PACKED1:0][P_PACKED2:0][0:P_UNPACKED0][0:P_UNPACKED1]

This also appears to be the case using the functions in utils.py, where only the first packed dimension is identified as the "width". I believe this may be a result of the previous Verilog specs only allowing a single packed dimension, however in SystemVerilog multiple packed dimensions are allowed.

How HDLConvertorAst support SystemVerilog? Only find SystemC、verilog 、 vhdl and others in https://github.com/Nic30/hdlConvertorAst/tree/master/hdlConvertorAst/to

Hi, I was trying to convert back with ToVerilog2005() and a localparam with operator ** failed.

I think it is a typo at:

`~/anaconda3/envs/jupyter/lib/python3.8/site-packages/hdlConvertorAst-0.4-py3.8.egg/hdlConvertorAst/to/common.py in _precedence_of_expr(self, o)
85 if not isinstance(o, HdlOp):
86 return (-1, ASSOCIATIVITY.NONE, None)
---> 87 return self.OP_PRECEDENCE[o.fn] + (o.fn, )
88
89 def visit_HdlOp(self, op):

KeyError: <HdlOpType.POW: 27>`

Let me know if more info or an example is required.
Thanks,
Danilo.

Hello,
I want to use HDL AST to generate Verilog (not System Verilog), but I am worried that whether the converted file will have System Verilog specific syntax. I see the class name in the code is "ToVerilog2005", and I know Verilog2005 is a subset of SystemVerilog. So, I just guess that you are using Verilog2005 to be compatible with both Verilog and SystemVerilog. Is my guess correct? If not, how could I get the pure Verilog code (not System Verilog)?
Thank you so much.