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Simulation only cartridge NeoGeo hardware definition

License: GNU General Public License v3.0

Verilog 74.85% C 1.92% VHDL 21.85% Batchfile 0.01% VBA 1.37%
arcade chip fpga logic mvs neo-geo neogeo simulation snk verilog

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emudrache z5ottu santabomber fejiso gwsu gongfna marcellodash bhamadicharef cam900 kenkieo sihai90 simrit1

neogeofpga-sim's Issues

How to generate the ROM files?

Hello.
I've been trying to get the design to compile with Quartus.
I generated the ROM files for
rom_sp-u2_fast.txt (from what MAME refers to as sp-u2.sp1) using word-wise encoding (I know it's sp-s2 originally, but I only have the US version).
and
rom_l0.txt (from what MAME refers to as 000-lo.lo) using byte-wise encoding.
But the sizes of the files are double or half of what the design expects.
So I guess I'm doing something wrong there?

Warning (10850): Verilog HDL warning at rom_sp.v(15): number of words (65536) in memory file does not match the number of elements in the address range [0:131071]

and at the same time the l0 ROM is too big.

Warning (10850): Verilog HDL warning at rom_l0.v(15): number of words (131072) in memory file does not match the number of elements in the address range [0:65535]

EDIT: Both are 128KB big, and rom_sp expects 16-bit big values while l0 expects 8-bit, so it is strange that according to the expected address range they're both swapped.

sdram running too slow

can we have option's to run sdram at different speeds mine runs upto 167mhz might have less glitching then

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